15-410
“...Everything
old is new again...”
Scheduling
Mar.
15, 2004
Dave Eckhardt
Bruce Maggs
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L20a_Scheduling
15-410, S’04
Synchronization
Checkpoint
2 details22
Monday,
Watch forMarch
Final You
Exam
list
posted
must
notify
of conflicts in a timely fashion
Today
would
be us
good
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15-410, S’04
Outline
Chapter 6: Scheduling
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CPU-I/O Cycle
Process
view:
2I/O
states
Running
Waiting
for
LifeI/O
Cycle
(loading executable), CPU, I/O, CPU, .., CPU (exit())
System
view – not enough processors for you right now
Running,
Runnable Waiting
Running
waiting
is mostly
voluntary
How 
long
do processes
choose
to run before waiting?
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CPU Burst Lengths
Overall
Exponential fall-off in CPU burst length
100
90
80
70
60
50
40
30
20
10
0
-1-
0
5
10
15
20
25
30
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CPU Burst Lengths
“CPU-bound”
program
Batch
job bursts
Long CPU
100
90
80
70
60
50
40
30
20
10
0
-1-
0
5
10
15
20
25
30
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CPU Burst Lengths
“I/O-bound”
program
Copy,
Data
acquisition,
... system calls
Tiny CPU
bursts
between
100
90
80
70
60
50
40
30
20
10
0
-1-
0
5
10
15
20
25
30
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Preemptive?
Four A
opportunities
towaits
schedule
running
process
(I/O, child, ...)
A
running
process
exits
A
waiting
process
becomes
runnable (I/O done)
Other interrupt (clock, page fault)
Multitasking
typesonly
Fully
Preemptive:
Allfirst
four two
cause scheduling
“Cooperative”:
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Preemptive kernel?
Preemptive
multitasking
All four cases
cause context switch
Preemptive
kernel
All
four
cause
context
switch
inwhen
kernel
mode
This
is acases
goal
of
Project
3disabling
System
calls:
interrupt
only
really
necessary
Clock interrupts should suspend system call execution
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CPU Scheduler
Invoked
when
CPU
becomes idle
Current
task
blocks
Clock interrupt
Select
next task
Quickly
PCB's in: FIFO, priority queue, tree, ...
Switch
(using
“dispatcher”)
Your
term may
vary
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Dispatcher
Set down
running
task
Save
register
state
Update
CPU
usage
information
Store PCB in “run queue”
Pick up
designated
task
Activate
new task's
memory
Protection,
mapping
Restore
register
state
Transfer to user mode
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Scheduling Criteria
System
administrator
view
Maximize/trade
off
CPU
utilization
(“busy-ness”)
Throughput
(“jobs
per second”)
Process
view timetime
Minimize
Turnaround
(everything)
Waiting
(runnable
but not running)
User Minimize
view (interactive
processes)
response time (input/output latency)
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Algorithms
Don'tFCFS
try these at home
SJF
Priority
Reasonable
Round-Robin
Multi-level (plus feedback)
Multiprocessor, real-time
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FCFS- First Come, First Served
BasicRun
idea
task
until it relinquishes
CPU
When
runnable,
place at end of
FIFO queue
Waiting time very dependent on mix
“Convoy
effect”
N
tasks
each make
I/O request,
stall
1 task
executes
very1 long
CPU burst
Lather,
rinse, repeat
N “I/O-bound
tasks” can't keep I/O device busy!
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SJF- Shortest Job First
BasicChoose
idea up CPU
withsoonest,
shortest be
next
CPU burst
Will givetask
“nicest”
to other tasks
Provably
“optimal”
Minimizes
average
waiting
time across tasks
Practically
impossible
(oh,
well)
Could
predict
next
burst
length...
»» Text
presents
exponential
average
Does not present evaluation
(Why not? Hmm...)
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Priority
BasicChoose
idea
“most important”
waiting
task
(Nomenclature:
does “high
priority”
mean p=0 or p=255?)
Priority
assignment
Static:
fixed
property
(engineered?)
Dynamic:
function
of task
behavior
Big problem:
Starvation
“Most
run often
“Leastimportant”
important “task
taskgets
maytonever
run
Possible hack: priority “aging”
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Round-Robin
BasicRun
idea
each
task for
a fixedappend
“time quantum”
When
quantum
expires,
to FIFO queue
“Fair”But not “provably optimal”
Choosing
quantum
length
Infinite
(until (1
process
does I/O)
= FCFS sharing”
Infinitesimal
instruction)
= “Processor
Balance “fairness” vs. context-switch costs
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True “Processor Sharing”
CDC Peripheral Processors
Memory
latency
Long,
fixed constant
Every instruction
Solution:
round
robin
Quantum
= 1 instruction
Memory
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Register Set
Register Set
Register Set
Register Set
Register Set
Processor Core
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True “Processor Sharing”
CDC Peripheral Processors
Memory
latency
Long,
fixed constant
Every instruction
Solution:
round
robin
Quantum
= 1 instruction
One “process”
running
Memory
N-1 “processes” waiting
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Register Set
Register Set
Register Set
Register Set
Register Set
Processor Core
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True “Processor Sharing”
Each“Brief”
instruction
computation
OneSleeps
load
xor
one store
process
N cycles
Steady
state
Run
when
ready
Ready
when
it's your turn
Memory
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Register Set
Register Set
Register Set
Register Set
Register Set
Processor Core
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Everything Old Is New Again
Intel “hyperthreading”
N
sets
M register
functional
units
Switch
on long-running
operations
Sharing
regular
Sharing
illusion
more
lumpy
Good less
for some
application
mixes
Memory
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Register Set
Register Set
Register Set
Register Set
Register Set
Processor Core
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Multi-level Queue
N independent
process queues
One
per priority
Algorithm
per-queue
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Priority 0 P1
P7
R. Robin
Priority 1 P2
P9
P3 R. Robin
Batch
P4
FCFS
P0
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Multi-level Queue
Inter-queue
scheduling
Strict
priority
Prislicing
0 runs
before
Pri 1, Pri 1round-robin)
runs before batch – every time
Time
(e.g., weighted
Pri
0
1 gets
1 1slices
slice
Batch
gets2
slice
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Multi-level Feedback Queue
N queues, different quanta
Exhaust
yourpriority
quantum?
Demoted
to
slower queue
Longer
quantum
Lower
Can you
beyou
promoted
back
Maybe
promotes
you up?
Maybe I/O
“age” upward
Popular “time-sharing” scheduler
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Multiprocessor Scheduling
Common
assumptions
Homogeneous
processors
(same speed)
Uniform memory
access (UMA)
LoadSingle
sharing
/ Load
global
readybalancing
queue – no false idleness
Processor
Affinity
Some» processor
be more desirable or necessary
Special I/O may
device
» Fast thread switch
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Multiprocessor Scheduling - “SMP”
Asymmetric
multiprocessing
One
processor
is “special”
Executes
all
kernel-mode
instructions
Schedules
other
processors
“Special”
aka
“bottleneck”
Symmetric
multiprocessing - “SMP”
“Gold
Tricky standard”
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Real-time Scheduling
Hard System
real-time
always
meet
performance
goals
Or it'smust
broken
(think:
avionics)
Designers
must
describe
task
requirements
Worst-case
execution
time
of instruction sequences
“Prove”
system
response
time
Argument
or
automatic
verifier
Cannot
use
indeterminate-time
technologies
Disks!
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Real-time Scheduling
Soft real-time
“Occasional”
deadline
CNN playback
video clip
onPC
PC failures tolerable
DVD
on
Much
than
real-time
Real-time
extension
to
timesharing
»cheaper
POSIX
real-time
extensions
for OS
Unix
Can
estimate
(vs. hard
prove)
task needs
Priority
scheduler
Preemptible OS
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Scheduler Evaluation Approaches
“Deterministic
modeling”
aka “hand execution”
Queueing
theory
Math
big fast
Math »gets
sensitive
to assumptions
May be unrealistic
(aka “wrong”)
Simulation
Workload
model
or trace-driven
GIGO hazard
(either
way)
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Summary
Round-robin
is of
okof
for
cases
Certainly
80%
the simple
conceptual
weight
Certainly
good
enough
for
P3
Speaking
P3...
» Understand preemption, don't evade it
“Real”
systems
Some
multi-level
feedback
Probably
some soft
real-time
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