The CMU Reconfigurable
Computing Project
April 9, 1999
Mihai Budiu
mihaib@cs.cmu.edu
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Current Project Members
CS Department
ECE Department
Seth Copen Goldstein
Mihai Budiu
Herman Schmit
Srihari Cadambi
Matt Moe
Robert Taylor
Ronald Laufer
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Why Study Reconfigurable Hardware?
It is a nice computation paradigm
(wire your own computer)
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Why Study Reconfigurable Hardware
Algorithm Year System
Versus Speedup x
DNA matching
1992
SPLASH 2
SPARC 10
4300
FIR Filter
1998
PipeRench
90
IDEA Encryption
1998
SAT solver
1997
Ray Casting
1995
Hidden Markov
Model
DES Encryption
1996
UltraSparc
300Mhz
PipeRench
UltraSparc
300Mhz
Pamette
SPARC 5
110Mhz
RIPP-10
Pentium
75Mhz
1 Xilinx FPGA SPARC 10
1996
GARP
SPEC92
1994
MIPS+RC
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UltraSparc
170Mhz
MIPS
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17--1100
33.8
24.4
24
1.22
4
Commercial Players
Source: In-stat April 1998
*Does not include software, hardwire or support EPROMs
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What Is “Reconfigurable Hardware?”
Interconnection
network
Universal gates
and/or
storage elements
Switches
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Basic Ingredient: RAM cell
a0
a1
0
0
0
1
data
a0
a1
a1 & a2
Universal gate = RAM
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Basic Ingredients (ctd)
1
0
1
1
A switch is controlled by a 1-bit RAM cell
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Outline
•
•
•
•
What is reconfigurable hardware
RH vs other computation paradigms
Challenges in RH research
PipeRench: the CMU project:
– the hardware
– the software
• Conclusions
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RH vs ASICs
• Generally Application-Specific Integrated Circuits
will be faster than RH:
– RH wires are slow & big
– RH bit-slices are costly to interconnect
– RH devices must store configuration on the chip
but
• RH can be reprogrammed
– new algorithms
– to fix bugs
• RH cheaper in small production
• RH tolerates faults better
• RH sometimes faster with staged computation
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RH vs Microprocessors
• RH less flexible (like a VLIW with fixed
instructions)
but
• RH provides more (customized)
computation elements
• RH can decrease memory traffic
• RH can be tailored for specific algorithms
and data types
RH will not replace mP, but complement them
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Types of RH
• FPGAs: bit-level logic functionality
(the basic processing elements compute on 1 bit)
• word-based architectures: PipeRench (CMU)
(basic PE operates on 8 bits)
(basic PE is a small ALU)
• coarse architectures: RAW (MIT)
(basic PE is a MIPS 2000 core)
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RH In A System
Title:
(c oupling)
Creat or:
(FrameMaker 5.5 Pow erPC: Las erWrit er 8 8.5. 1)
Prev iew :
This EPS pict ure w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS pict ure w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
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Challenges In RC
• Software tools:
– Programming RC like software development
– Automatic compilation from HLL
– Automatic program partitioning
• Mapping efficiently algorithms (no ISA)
• System issues
– interfaces
– find “ideal” RC fabric
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The CMU Reconfigurable
Computing Project
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Hardware Goals
• To build a complete reconfigurable
hardware device
• To build the system integration hardware
• To host the device in a PC
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Our Device:
•
•
•
•
•
Word processing elements
Pipelined architecture
Virtualized hardware
Local interconnection network
Wide pipelined bus
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Configuration
memory
Data & Config
controller
Stripes
Processing
elements
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Hardware Virtualization
Actual available
hardware
Instructions
currently in hardware
Instructions paged out
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Hardware Virtualization (2)
Page out
compute
compute
compute
configure
Page in
hardware
Program in
configuration
memory
Overlap configuration
with computation.
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Processing Elements
a
PE2
b
PE1
out
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Cin
PE0
• Look-up table
• Any 3-to-1 function
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The Interconnection Network
P*B bits
Word-level cross-bar
0
B bits
PE N
PE
PE 1
Pass Registers
P*B*N bits
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The PCI Board
Title:
c hip.eps
Creat or:
f ig2dev Version 3.2 Patchlevel 0-beta3
Prev iew :
This EPS pict ure w as not s av ed
w ith a preview inc luded in it.
Comment:
This EPS pict ure w ill print to a
Pos tSc ript printer, but not to
other ty pes of printers.
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Software Goal
To program reconfigurable devices using the
standard software development processes:
Java
– Compile C or Java
– Do it quickly
Partitioner
Data-flow Intermediate
Language
DIL
Built
Configuration
Reconfigurable HW
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CPU
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Building Circuits From DIL
a = b + c * d;
e = c - d;
c
b
d
*
• variables
• operators
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wires
gates
+
-
a
e
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Mapping Circuits To
a
a
b c
b c
+
a
c
b
+
+
-
a
+
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c
b
-
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The DIL Compiler Front-End
Circuit
Dil
input file
Parser
Evaluator
Loader
Backend
Loader
component
library
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Component
circuits
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The DIL Compiler Backend
Circuit
(expanded)
Front-end
Circuit
(placed)
Circuit
Optimizer
PlacerRouter
The whole compilation process is
very fast (compared to classical
CAD tools).
We can compile two orders of
magnitude faster.
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Code generator
xfig
C++
Asm
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Processing Element Size Tradeoffs
Small
Efficient usage
Slower
Flexible interconnect
Bigger configuration
Place and route easier
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Big
Wasteful
Faster bit-slice
Coarse routing
Fewer configuration bits
Constrains the compiler
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Stripe Width Tradeoffs
Wider
Fewer stripes
Virtualize more
Bandwidth waste
Placer freedom
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Narrower
More will fit
Fewer page-ins
Less bandwidth available
Placement constrained
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Bus Width Tradeoffs
Wider
More area
High bandwidth
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Narrower
Less area
Time-mux bus
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Clock Speed Tradeoffs
(run-time)
Faster
Short critical path
Long pipeline built
Decomposition overhead
Virtualized more
24
Little decomposition
Less virtualized
24
8
+
8
+
+
Slower
Big chains
Compact circuits
24
24
+
24
8
24
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Configuration Bits per Stripe
2
1600
4
PE bit width
8 16 32
128
144
Configuration Bits
1400
1200
1000
800
600
400
200
0
64
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80
96
112
Stripe Width
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Title:
(fir-throughput.eps)
Creator:
Adobe Illus trator(TM) 7.0
Preview :
This EPS picture w as not saved
w ith a preview included in it.
Comment:
This EPS picture w ill print to a
PostScript printer, but not to
other ty pes of printers .
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Project Status
• Operational:
– Behavioral and structural models of Piperench
in Verilog
– Assembler, simulator
– Tools for visualization and debugging
– One tile fabricated and tested
– Very fast compiler from intermediate language
• In work:
– Prototype PipeRench to be taped this summer
– PCI board to host PipeRench in a PC
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Simulated Speed-up vs. UltraSparc @ 300Mhz
1000.0
328.8
90.9
100.0
76.1
61.8
29.0
26.0
20.6
10.0
1.0
ATR
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Cordic
DCT
FIR
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IDEA
Nqueens
Over
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Future Work
• Build the PCI board
• Build the OS device drivers
• Start investigating HLL issues:
– automatic partitioning
– translation to DIL
– special code transformations
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Conclusions
• A set of important applications can benefit from
RC devices
• RC offer potential for substantial performance
improvement at a low cost
• RC devices will soon be mainstream U
in the embedded computing world;
V
perhaps in the future they will also
R
permeate the desktop
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Pentium V
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