N Combinational Circuits Master’s Defense Kalyana R. Kantipudi

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Minimizing N-Detect Tests for
Combinational Circuits
Master’s Defense
Kalyana R. Kantipudi
Thesis Advisor: Dr. Vishwani D. Agrawal
Thesis Committee: Dr. Charles E. Stroud and Dr. Victor P. Nelson
Dept. of ECE, Auburn University
Nov 29th 2006
MS Thesis Defense
1
Outline
• Background
• Problem Statement
• Contributions
Theoretical Minimum for N-Detect Tests
ILP Based N-Detect Test Minimization
Relaxed LP based methods
The New Recursive Rounding Approach
• Conclusions
Future work
Nov 29th 2006
MS Thesis Defense
2
Background
• Defects are modeled as faults
• Single stuck-at faults ease the test generation process
• Bridging faults emulate the defects more accurately
K=1
W sa1
1
OR
W
0
AND
K=0
Dominate
K=1
K=0
W sa0
• Test sets with greater than 95% fault coverage can produce only
33% coverage of node-to-node bridging faults (Krishnaswamy et al. ITC’01)
• About 80% of all bridges occur between a node and Vcc or Vss
Nov 29th 2006
MS Thesis Defense
3
N-Detect Tests
• Some applications need much lower DPM
• New test strategy which can be easily assimilated
into the normal test generation process
• The problem with N-detect tests is their size
• There is no accurate way to achieve a minimal Ndetect set
• There is no proven lower bound on the size of the
N-detect vectors
Nov 29th 2006
MS Thesis Defense
4
Problem Statement
• To find a lower bound on the size of N-detect tests
• To find an exact method for minimizing a given
N-detect test set
• To derive a polynomial time heuristic algorithm for
the N-detect test minimization problem
Nov 29th 2006
MS Thesis Defense
5
The Independence Graph
• Independence graph: Nodes are faults and edges
represent pair-wise independence relationships
• A clique is a fully connected sub-graph
Example: c17
1
2
3
4
5
11
11
6
7
8
9
10
A. S. Doshi, “Independence Fault Collapsing and Concurrent Test Generation,”
Master’s thesis, Auburn University, May 2006.
Nov 29th 2006
MS Thesis Defense
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Lower Bound on Single-Detection Tests
• The Independent Fault Set (IFS) is a maximal clique in
the graph
• Theorem 1: The size of the IFS is a lower bound on the
single detection test set size (Akers et al., ITC-87)
1
2
3
4
5
1
11
6
7
8
9
4
10
2
5
So, the lower bound for the single detection test set of c17 is ‘4’.
Nov 29th 2006
MS Thesis Defense
7
Theoretical Minimum of an
N-Detect Test Set
• Theorem 2: The lower bound on the size of the N-detect
test set is N times the size of the largest clique in
the independence graph (Original Contribution)
N test
Vecs
N test
Vecs
1
N test
Vecs
1
4
2
5
N test
Vecs
So, at least 4N vectors are needed to
detect each fault ‘N’ times.
Nov 29th 2006
MS Thesis Defense
8
Minimized N-Detect Vectors for
74181 ALU
Nov 29th 2006
N
Lower Bound
(Theorem 2)
Minimized from
Exhaustive set
1
12
12
10
120
120
20
240
240
30
360
360
40
480
480
50
600
607
60
720
742
70
840
877
80
960
1012
90
1080
1147
96
1152
1228
MS Thesis Defense
9
ILP Based N-Detect Test Minimization
• Use any N-detect test generation approach to obtain a
set of k vectors which detect every fault at least N times.
• Use diagnostic fault simulation to get the vector subset
Tj for each fault j.
• Assign integer variable ti to ith vector such that,
 ti = 1 if ith vector is included in the minimal set.
 ti = 0 if ith vector is not included.
Nov 29th 2006
MS Thesis Defense
10
Objective and Constraints of ILP
k
Objective : minimize
t
i 1
Constraints :
t
i
vectori  T j 
i
 N j ,  faults j
Nj is the multiplicity of detection for the jth fault.
Nj can be selected for individual faults based on some
criticality criteria or on the capability of the initial
vector set.
Theorem 3: When the minimization is performed over an
exhaustive set of vectors, an ILP solution that satisfies
the above expressions is a minimum N-detect test.
Nov 29th 2006
MS Thesis Defense
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Derivation of N-Detect Tests
• Generate an unoptimized M-detect test set (M  N) using
an ATPG (e.g., ATALANTA).
• Remove repeated vectors.
• Perform diagnostic fault simulation of the remaining vectors
using a fault simulator (e.g., HOPE).
• If |Tj | < N for any fault, obtain additional vectors for that
fault.
• Generate ILP constraints and use an ILP solver to
determine the values of the variables ti that minimize the
number of vectors = Σti .
Nov 29th 2006
MS Thesis Defense
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Minimal 3-Detect Test Set for c17
sa1
9x
sa1
14
x
sa1
x8
sa1
7x
sa1
13
x
sa1 sa1
11
x X 15
x
sa0
10
sa1
17
x
sa1
X x3
12
sa0
Fault Numbers
sa1
20
x
sa1
16
Xx
4
sa0
sa1
21
x
sa1
x2
sa1
X6x
sa0
1
sa1
x
X18
5
sa0
sa1
19
x
sa1
22
x
• ATALANTA is used to generate 4 test sets (M = 4 iterations) and
the repeated vectors are removed.
• HOPE is used to perform diagnostic fault simulation on the
remaining vectors.
• The simulation information is used to create constraints for the ILP
Nov 29th 2006
MS Thesis Defense
13
Constraint Generation
• Fault 1 is detected by the vectors 1, 2, 15, 16, 22, 24.
• Fault 2 is detected by the vectors 1, 2, 3, 4, 5, 6, 7, 8, 9, 15,
16, 22, 24, 28, 29.
.... so on ....
29
Now the Objective is: minimize  t i
i 1
and the constraints are:
t
i
vectori  T j 
 3,  faults j
Constraint for fault 1: t1+t2+t15+t16+t22+t24 ≥ 3
Constraint for fault 21: t13+t15+t16+t19+t23+t24 ≥ 3
Nov 29th 2006
MS Thesis Defense
14
Minimum Test Sets from ILP
• The minimum 3-detect test set size is 13 (lower bound = 12).
 Vectors are: 2, 6, 7, 11, 14, 15, 16, 17, 18, 21, 23, 24, 28.
Suppose ‘fault 21’ is a critical fault to be detected 5 times:
Constraint for fault 21: t13+t15+t16+t19+t23+t24  5
3
• The minimum test set given by ILP has 14 vectors.
 Vectors are: 2, 6, 7, 11, 12, 13, 14, 15, 16, 17, 18, 19, 23, 28.
For large circuits this change in test size can be quite small.
Nov 29th 2006
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15
Results
Single Detection
Circuit No. of
Name Un Opt.
2-Detect
3-Detect
5-Detect
Vecs
ILP Time
(sec.s)
Lower
bound
Set
Size
Lower
bound
Set
Size
Lower
Bound
Set
Size
Lower
Bound
Set
Size
c432
14882
82.3
27
27
54
55
81
83
135
140
c499
397
5.34
52
52
104
104
156
156
260
260
c880
3042
306.81
13
25
26
44
39
63
65
105
c1355
755
16.71
84
84
168
168
252
252
420
420
c1908
2088
97
106
106
212
212
318
318
530
530
c2670
8767
*1568.62
44
71
88
145
132
224
220
391
c6288
243
519.67
6
18
12
27
18
37
30
57
c7552
2156
*1530
65
148
130
298
195
468
325
841
Results on Ultra-5
Nov 29th 2006
MS Thesis Defense
* Ultra-10
16
Results for 15-Detect Tests
ILP
Circuit
Prev. Result [1]
No. of
CPU s vectors
No. of
vectors
CPU s
Lower
Bound
15 x [2]
c432
444.8
430
292.1
505
405
c499
24.9
780
153.2
793
780
c880
521.4
321
229.6
338
195
c1355
52.0
1260
5674.6
1274
1260
c1908
191.0
1590
1563.9
1648
1590
c2670
*607.8
1248
9357.6
962
660
c3540
1223.7
1411
-
-
1200
c5315
*1368.4
924
-
-
555
c6288
1206.3
134
1813.8
144
90
c7552
**346.1
2370
-
975
c499, c1355, c1908 - Type – I
C880,c2670,c7552 - Type – II
Results on Ultra-5
* Ultra-10
** Sun Fire 280R
[1] Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002
[2] Hamzaoglu and Patel, IEEECAD, 2000.
Nov 29th 2006
MS Thesis Defense
17
Minimized Vectors for 15-Detect Tests
2000
1500
Lower Bound
Present (ILP)
1000
Previous
500
Nov 29th 2006
MS Thesis Defense
c7
55
2
c5
31
5
c6
28
8
c2
67
0
c3
54
0
c1
35
5
c1
90
8
c8
80
c4
99
0
c4
32
Test Set Size (Vectors)
2500
18
CPU Time for Minimizing 15-Detect Tests
Time Taken (Seconds)
10000
9000
8000
7000
6000
5000
4000
3000
Present (ILP)
Previous
2000
1000
0
3
c4
Nov 29th 2006
2
9
c4
9
8
c8
0
35
1
c
5
90
1
c
8
67
2
*c
0
54
3
c
0
31
5
*c
MS Thesis Defense
5
52
88
5
2
c7
c6
**
19
Classifying Combinational Circuits
TYPE – II:
TYPE - I:
F1
P
PO1
X
P
F1
R
R
X
I
I
Output cones
have large overlap.
Non-overlapping
output
cones.
PO1
M
M
A
F3
A
PO2
X
X
R
Any
vector
detecting
a
fault
F2
Any
vector
detecting
a
particular
R
F2
Y
`
Y
will have high probability of
PO2
fault, will have very low probability
Iof
N
P
U
T
S
I
N
P
U
T
S
F2
X
X
detecting
any other fault.detecting other faults, say fault
F3
F3 or F1.
PO3
F4
X
F4 X
c499, c1355, c1908
Nov 29th 2006
PO3
PO4
c880, c2670, c7552
MS Thesis Defense
20
Ripple Carry Adders
1-b
Ci+1
1-b
1-b
Ai
Si
Bi
Ci
Iterations: Number of times test sets
are taken from Atalanta ATPG
Nov 29th 2006
MS Thesis Defense
1-b
21
Relaxed-LP Approach
• Though ILP guarantees an optimal solution, it takes
exponential time to generate the solution.
• Time bounded ILP solutions deviate from optimality.
• LP takes polynomial time (sometimes in linear time) to
generate a solution.
• Redefining the variables tis as real variables in the range
[0.0,1.0] converts the ILP problem into a linear one.
• The problem now remains to convert it into an ILP
solution.
 The optimal value of the relaxed-LP of the ILP minimization
problem is a lower bound on the value of the optimal integer
solution to the problem.
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MS Thesis Defense
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Previous Solutions (Randomized Rounding)
• The real variables are treated as probabilities.
• A random number xi uniformly distributed over the
range [0.0,1.0] is generated for each variable ti.
• If ti ≥ xi then ti is rounded to 1, otherwise rounded to 0.
• If the rounded variables satisfy the constraints, then the
rounded solution is accepted.
• Otherwise, rounding is again performed starting from
the original LP solution.
Nov 29th 2006
MS Thesis Defense
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Limitations of Randomized Rounding
• Consider three faults f1,f2 and f3, and three vectors.
• We assign a real variable ti to vector i.
• Now the single detection problem is specified as:
t3
 Minimize t1 + t2 + t3
1
 Subject to constraints,
 f1 : t1 + t2 ≥ 1
LP Solution
 f2 : t2 + t3 ≥ 1
(0.5,0.5,0.5)
 f3 : t3 + t1 ≥ 1
t2
0
1
• The number of tests is much larger
1
than the size of the minimal test set.
t1
• The randomized rounding becomes a random search.
Nov 29th 2006
MS Thesis Defense
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Recursive Rounding (New Method)
• Step 1: Obtain an LP solution.
Stop if each ti is either 0.0 or 1.0
• Step 2: Round the largest ti and fix its value to 1.0
If several ti’s have the largest value, arbitrarily
set only one to 1.0. Go to Step 1.
 Maximum number of LP runs is bounded by the final
minimized test set size.
 Final set is guaranteed to cover all faults.
 This method takes polynomial time even in the worst case.
 LP provides a lower bound on solution.
Lower Bound ≤ exact ILP solution ≤ recursive LP solution
Absolute optimality is not guaranteed.
Nov 29th 2006
MS Thesis Defense
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The 3V3F Example
• Step 1:
t3
LP gives t1 = t2 = t3 = 0.5
1
• Step 2:
We arbitrarily set t1 = 1.0
Non-optimum
solution
• Step 1:
Gives t2 = 1, t3 = 0 ■
or t2 = 0, t3 = 1 ■
or t2 = t3 = 0.5
LP Solution
(0.5,0.5,0.5)
0
t2
1
1
• Step 2: (last case)
Step 1
We arbitrarily set t2 = 1.0
Step 2
• Step 1: Gives t3 = 0
Nov 29th 2006
ILP solutions
(optimum)
MS Thesis Defense
t1
26
Minimal Tests for Array Multipliers
• There exists a huge difference
between its theoretical lower bound
of six and its practically achieved test
set of size 12.
• A 15 x 16 matrix of full-adders (FA) A B
and half-adders (HA).
F
A
A B
• To make use of its recursive
structure and apply
F
n-2
3
A
A B
linear programming
F
F
techniques.
P2n-1P2n-2
Nov 29th 2006
n-2
2
1 H
1 A
F
A
1 F
2 A
A0
B2
P2
F
A
1 F
3 A
A0
B3
P3
A
H
A
Pn+1
Pn
MS Thesis Defense
H
A
A1B0
P1
n-1 2
A
n-2
1
H
A
n-1 1
n-1 n-1
A2B0
An-1B0
27
A0B0
P
A0 0
B1
Tests for c6288: 16-Bit Multiplier
• Known results (Hamzaoglu and Patel, IEEE-TCAD,
2000):
• Theoretical lower bound = 6 vectors
• Smallest known set = 12 vectors, 306 CPU s
• Our results:
• Up to four-bit multipliers need six vectors
• Five-bit multiplier requires seven vectors
• c6288
900 vectors constructed from optimized vector sets of smaller
multipliers
ILP, 10 vectors in two days of CPU time
Recursive LP, lower bound = 7, optimized set = 12, in 301 CPU s
Nov 29th 2006
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Comparison of ILP and Recursive LP method
180
160
21
18
120
100
15
80
12
60
9
40
6
20
0
3
3
4
5
6
7
8
9
10
Bit Multiplier (Bits)
Nov 29th 2006
MS Thesis Defense
11
12
Test Set Size (Vectors)
140
CPU Seconds
LP CPU
Secs
24
ILP CPU
Secs
LP Set size
ILP Set
size
Time
bound ILP
Set size
1000 sec
29
Sizes of 5-Detect Tests for ISCAS85 Circuits
900
Test Set Size (Vectors)
800
700
600
LB from LP
LP/Randomized
500
LP/Recursive
ILP Vecs
400
300
200
100
0
99
c4
Nov 29th 2006
80
c8
67
c2
0
54
c3
0
31
c5
5
28
c6
MS Thesis Defense
8
55
c7
2
30
Time Taken for 5-Detect Tests
881
140
20008
34740
CPU Seconds
120
100
80
LP/Randomized
LP/Recursive
ILP CPU s
60
40
20
0
99
c4
Nov 29th 2006
80
c8
67
2
c
0
54
3
c
0
31
5
c
5
28
6
c
MS Thesis Defense
8
55
7
c
2
31
Optimized 15-Detect Tests
Circuit Unopti.
Name
Vecs
LP/recursive
Rounding
Previous
Result [1]
ILP
Vect.
CPU s
Vect.
CPU s
Vect.
CPU s
L.B.
c432
14882
430
83.5
430
444.8
505
292.1
405
c499
1850
780
17.8
780
24.9
793
153.2
780
c880
4976
322
94.5
321
521.4
338
229.6
195
c1355
2341
1260
41.2
1260
52.1
1274
5674.6
1260
c1908
6609
1590
150.4
1590
191
1648
1563.9
1590
c2670
8767
1248
380.6
1248
607.8*
962
9357.6
660
c3540
4782
1407
239.6
1411
1223.7
-
-
1200
c5315
4318
924
494.3
924
1368.4*
-
-
555
c6288
731
134
250.5
134
1206.3
144
1813.8
90
c7552
6995
2371
359.1
2370
346.1**
-
-
975
[1] Lee, Cobb, Dworak, Grimaila and Mercer, Proc. DATE, 2002
Nov 29th 2006
MS Thesis Defense
32
Conclusion
• A Lower Bound for N-Detect tests is derived.
• An N-Detect test minimization method based on ILP is
formulated which always guarantees optimality.
• A polynomial time consuming recursive rounding LP, which
can give close to optimal solutions for single and N-detect
tests is presented.
• A smallest ever, 10 vector set derived for c6288 signifies
the shortcomings of present test minimization techniques.
• The new recursive rounding LP method has numerous
other applications where ILP is traditionally used and is
found to be expensive.
Nov 29th 2006
MS Thesis Defense
33
Future Work
• The dual problem of the test minimization problem
looks promising.
• The dual problem:
p
Objective function : maximize  fi
i 1
Constraints :
f  1,  vectors j

 
i
fi  F j
fi  0,1
• The Duality Theorem: If m is the minimum value of
the primal problem and M is the maximum value of
the dual problem, then m = M.
Nov 29th 2006
MS Thesis Defense
34
The Previous c17 Example
• The primal problem gave a solution of 4 vectors.
• The dual problem also gave a solution of 4, selecting
faults 1, 10, 16 and 18.
• It is observed that these four faults are independent
of each other.
• So the dual problem yielded an IFS of the circuit.
• In cases where relaxed-LP gives non-integer
solutions for the dual problem, rounding techniques
can be used.
 This new approach has the potential of generating
much tighter lower bound compared to the IFS.
Nov 29th 2006
MS Thesis Defense
35
Thank You . . .
Nov 29th 2006
MS Thesis Defense
36
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