Partial Scan Design With
Guaranteed Combinational ATPG
Vishwani D. Agrawal
Agere Systems
Processor Architectures and Compilers Research
Murray Hill, NJ 07974
va@agere.com
Yong C. Kim and Kewal K. Saluja
University of Wisconsin, Dept. of ECE
Madison, WI 53706
kimy@ece.wisc.edu and saluja@engr.wisc.edu
October 5, 2001
Oct. 5, 2001
Agrawal, Kim and Saluja
1
Problem Statement


Partial scan design has less DFT overhead, but is
less desirable than full-scan because it requires
sequential ATPG.
Problem: To devise a combinational ATPG method
for general acyclic (cycle-free) circuits; cyclic
structures can be made acyclic by partial scan.
FF1
FF2
A cyclic circuit
Oct. 5, 2001
FF2
Acyclic partial scan circuit
Agrawal, Kim and Saluja
2
Overview
1. Combinational ATPG for general acyclic circuits




Background: Previous results and relevant ideas
Balanced model for combinational ATPG
Single-fault model for multiple-faults
Results
2. Special subclasses of acyclic circuits
 Background: Definitions and ATPG properties
 Examples
 Results
3. Conclusion
Oct. 5, 2001
Agrawal, Kim and Saluja
3
Previous Work: ATPG Models for Acyclic
Sequential Circuits
 Iterative array model (Putzolu and Roth, IEEETC,
1971)
 Duplicated fan-in logic model (Miczo, 1986)
 Duplicated logic model (Kunzmann and Wunderlich,
JETTA, 1990)
 Balanced structure (Gupta, et al., IEEETC, 1990)
 Pseudo-combinational model (Min and Rogers,
JETTA, 1992)
Oct. 5, 2001
Agrawal, Kim and Saluja
4
Two Relevant Results
 Theorem (Bushnell and Agrawal, 2000):
A test for a testable non-flip-flop fault in a
cycle-free (acyclic) circuit can always be found
with at most dseq+1 time-frames.
 Balanced circuit (Gupta, et al., IEEETC, 1990):
An acyclic circuit is called balanced if all paths
between any pair of nodes have the same
sequential depth. A combinational ATPG
procedure guarantees a test for any testable
fault in a balanced circuit.
Oct. 5, 2001
Agrawal, Kim and Saluja
5
An Example
Unbalanced nodes
a
s-a-0
s-a-0
b
FF
dseq =
1
Combinational
vector
Balanced model
a1
0
b1
X
s-a-0
0
Single fault
1 s-a-0
1/0
Multiple fault
a0
b0
1
s-a-0
1/0
1
1/0
FF replaced
by buffer
Test sequence: 11, 0X
Oct. 5, 2001
Agrawal, Kim and Saluja
6
A Combinational ATPG System for
General Acyclic Sequential Circuits
Generate a balanced model, map faults
Generate a test vector for a target fault using
combinational ATPG
Simulate the comb. model to drop detected
faults
More faults to be
detected?
No
Yes
Obtain a test sequence from comb. vectors
Oct. 5, 2001
Agrawal, Kim and Saluja
7
A Single-Fault Model for a Multiple-Fault
Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Multiple Faults:
Modeling, Simulation and Test,” 15th International Conf. on
VLSI Design, January 2002.
Multiple
stuck-at
fault:stuck-at
lines a fault:
and boutput
stuck-at
1 andgate
line
An
equivalent
single
of AND
c stuck-at
stuck-at
1 0.
s-a-1
s-a-1
aa
s-a-1
bb
cc
Oct. 5, 2001
s-a-0
Agrawal, Kim and Saluja
A
A
B
B
C
C
8
Proof of Correctness
 Circuit
equivalence:
Fault-free
output
functions
 
Fault
Fault
equivalence:
equivalence:
Faulty
Faulty
output
output
functions
functions
A = a + a ·b ·!c = a
AsfA=mf =
a +1 1 = 1
B = b + a ·b ·!c = b
BsfB=mf b=+11 = 1
C = c ·!(a ·b ·!c) = c · (!a + !b + c) =c ·(!a + !b) + c = c
CsfC=mf c=· 00 = 0
s-a-1
s-a-1
s-a-1
a
a
s-a-1
b
b
c
c
Oct. 5, 2001
s-a-0
Agrawal, Kim and Saluja
A
A
A
B
B
B
C
C
C
9
Acyclic Circuit Comb. ATPG Example
Step
Apply
DAS
to
PI
Amodeling.
and
B.
StepStep
1:
Levelization,
assign
weights
POs.
An
Example
Step
example
2:2:
3:
Balance
Replace
of Acyclic
multiple
with
FFs
circuit
respect
fault
with
with
buffers.
to to
PO
4to
FFs
Y.X.
Balance
with
respect
PO
A0
B0
A1
B1
1
0
A00
B00
s-a-1
s-a-1 1
11
1
1
Oct. 5, 2001
DQ
Q
D
FF2
FF2
FF2
FF211
1
55
FF3
FF3
DQ
Q
D
33
22
77
FF3
FF3
66
B222
B
C222
C
D111
D
s-a-1
s-a-1
s-a-1
s-a-1
A11
A
A
B11
1
0
D
Q
FF2
FF2
FF2 00
0
44
DQ
Q
D
FF4
FF4
X W(X)=2
X
X:
W(X) = 2
Y W(Y)=2
Y:
Y
W(Y) = 2
FF4
FF4
FF1
FF1
DQ
Q
D
FF1
FF1
Agrawal, Kim and Saluja
10
ISCAS ’89 Benchmark Circuit: S5378

Circuit statistics)



Number of gates: 2,781
Number of FFs:
179
Number of faults: 4,603
S5378
Scan-FFs
Overhead
Fault Eff.
ATPG Time
Original Full-scan
0
0%
70.9 %
5,533 s+
179
15.7 %
100.0 %
1s*
ATPG: Partial-scan
Sequential Combinational
30
30
2.6 %
2.6 %
99.7 %
99.7 %
1,268 s+
23 s*
ATPG run on Sun Ultra Sparc 10 workstation
+Gentest (seq. ATPG)
*TetraMax (comb. ATPG)
Oct. 5, 2001
Agrawal, Kim and Saluja
11
Acyclic Partial-Scan ISCAS’89 Circuits:
Test Generation Results
Circuit Sequential ATPG* Combinational ATPG
Name FC
FE TGT(s) FC
FE
TGT(s)
s5378
s9234
s13207
s15850
s35932
s38417
93.69 99.71 1268.0 93.69 99.71
93.16 99.94 426.0 93.16 99.94
97.13 99.97 1008.0 97.13 99.97
96.65 99.97 856.0 96.66 99.97
89.80 100.00 569.0 89.80 100.00
99.25 99.54 861.0 99.25 99.55
23.3
85.7
55.0
140.8
79.4
98.2
FC: cov. (%), FC: efficiency (%), TGT: CPU s Sun Ultra 10
*Gentest for seq. and TetraMAX for comb. ATPG
(Hitec produced equivalent FC, FE and TGT within 10% of Gentest)
Oct. 5, 2001
Agrawal, Kim and Saluja
12
Acyclic Partial-Scan ISCAS’89 Circuits:
Circuit Statistics
Circuit Total Scan Scan FFs Max Model Size
name FFs FFs
(%)
depth PI Gate
s5378
179
30
16.8
19 3.21 6.50
s9234
228 152
66.7
4 1.40 2.14
s13207
669 310
46.3
22 2.08 3.32
s15850
597 441
73.9
29 3.27 6.98
s35932 1728 306
17.7
34 2.33 3.80
s38417 1638 1080
69.9
9 1.13 1.64
s38584 1425 1115
78.2
35 2.32 4.13
Oct. 5, 2001
Agrawal, Kim and Saluja
MF
%
2.1
4.2
1.5
1.4
1.4
1.1
0.3
13
Background: Subclasses of Acyclic Circuits

Balanced (B) circuit: All paths between any pair of
nodes (PIs, POs, gates or FFs) have the same
sequential depth (Gupta, et al., IEEETC, 1990)

Strongly balanced (SB) circuit: A balanced circuit
having the same depth from a PO to all reachable PIs
(Balakrishnan and Chakradhar, VLSI Design’96)

Internally balanced (IB) circuit: Becomes
balanced by splitting of PI fanouts (Fujiwara, et al.,
IEEETC, 2000)
Sequential
Acyclic
IB
Oct. 5, 2001
B
SB
Combinational
Agrawal, Kim and Saluja
14
Examples of Acyclic Subclasses
An
AAStrongly
Internally
A Balanced
An example
Balanced
Balanced
structure,
Acyclic
structure,
structure,
requires
circuit
requires
requires
with
2 scan
FFs
1scan
FFs
scan
FFs
FF
Combinational
(Full-scan)
requires
4 3scan
FFs
FF2out
FF2out
FF3out
FF3out
A
A
FF2in
FF2in
FF3in
FF3in
B
B
C
C
FF4in
D
D
FF1in
Oct. 5, 2001
D
DQ
Q
11
55
DQ
FF2
FF2
FF3
66
33
22
77
44
D
DQ
Q
X
X
FF4out
Y
Y
FF4
FF4
FF1out
D
DQ
Q
FF1
FF1
Agrawal, Kim and Saluja
15
Number of Scan FFs for Acyclic Subclasses
Circuit
Name
s5378
s9234
s13207
s15850
s35932
s38417
s38584
Total
Average
No scan
Scan FFs
FFs
Acyclic
IB
B
SB Comb.
179
30
91
96
163
179
228
152
201
209
220
228
669
310
420
451
542
669
597
438
529
534
563
597
1728
306 1728 1728 1728
1728
1636
1115 1224 1232 1476
1636
1452
1115 1431 1431 1447
1452
6729
3618 5809 5866 6336
6729
0% 53.4% 78.3% 78.9% 87.2% 100.0%
IB: Internally balanced,
Oct. 5, 2001
B: Balanced,
Agrawal, Kim and Saluja
SB: Strongly balanced
16
Comb. ATPG Coverages for Acyclic Subclasses
FC
Acyclic IB
B
SB Comb.
s5378
93.69 98.77 98.78 98.81 98.87
s9234
93.16 93.47 93.47 93.95 93.95
s13207
97.13 98.43 98.46 98.87 98.87
s15850
96.66 96.68 96.68 97.51 97.51
s35932
89.80 89.81 89.81 89.81 89.82
s38417
99.25 99.46 99.47 99.53 99.68
s38584
95.46 95.52 95.52 95.54 95.57
Average
96.98 97.43 97.43 97.55 97.56
ATPG: TetraMAX
Gentest and Hitec produced similar coverages
Oct. 5, 2001
Agrawal, Kim and Saluja
17
ATPG CPU Seconds for Acyclic Subclasses
Circuit Acyclic IB
B
SB Comb.
s5378
23.3
0.6
0.6
0.4
0.2
s9234
85.7 66.7 64.6 64.6
64.6
s13207
55.0 21.8 20.0 26.5
26.5
s15850
140.8 115.6 113.7 113.2 112.3
s35932
79.4 70.1 70.0 70.8
70.8
s38417
98.2 24.2 24.2 24.8
24.8
s38584
239.6 30.1 30.2 28.9
28.0
Average
103.1 47.0 46.2 47.0
46.8
ATPG: TetraMAX (on Sun Ultra workstation)
Gentest and Hitec show similar proportions
Oct. 5, 2001
Agrawal, Kim and Saluja
18
Test Lengths for Acyclic Subclasses
Circuit
Name
Acyclic
VL
Internally Bal.
CC
VL
CC
Balanced
VL
Strongly Bal. Combinational
CC
VL
CC
VL
CC
s5378
1,230
371
912
83
912
88
580
95
580
104
s9234
1,680
256
1,138
236
1,138
238
727
161
766
175
s13207
3,126
9,701
2,328
1,040
2,328
1,051
1,238
673
1,355
909
s15850
5,780 25,331
1,785
946
1,785
955
1,192
673
1,192
713
s35932
7,548
2,311
2,319
4,012
2,319
4,012
2,320
4,014
2,319
4,012
s38417
8,632
9,628
4,863
7,143
4,863
7,168
3,329
4,918
3,384
5,541
12,231 13,641
7,722
11,055
7,722
11,055
3,645
5,279
3,627
5,271
s38584
VL: Number of combinational ATPG vectors
CC: Sequential test clock cycles (x1,000) for scan sequences
Oct. 5, 2001
Agrawal, Kim and Saluja
19
Conclusion
 Using a balanced circuit model and combinational
ATPG, we can generate tests for any acyclic
sequential circuit with equal or higher fault coverage
and efficiency than obtained by sequential ATPG.
 The proposed ATPG procedure provides comparable
fault coverage and efficiency with significantly lower
DFT (partial-scan) overhead as compared to
internally balanced, balanced, strongly balanced and
combinational subclasses.
 The multiple fault model has new applications to
diagnosis, logic optimization, multiply-testable faults,
and bridging faults (see VLSI Design’02 paper).
Oct. 5, 2001
Agrawal, Kim and Saluja
20
Papers
 Y. C. Kim, V. D. Agrawal and K. K. Saluja,
“Combinational Test Generation for Acyclic
Sequential Circuits using a Balanced ATPG Model,”
Proc. 14th Int. Conf. VLSI Design, Jan. 2001, pp. 143148.
 Y. C. Kim, V. D. Agrawal and K. K. Saluja,
“Combinational Test Generation for Various Classes
of Acyclic Sequential Circuits,” Proc. Int. Test Conf.,
Oct. 2001.
 Y. C. Kim, V. D. Agrawal and K. K. Saluja, “MultipleFaults: Modeling, Simulation and Test,” Proc. 15th
Int. Conf. VLSI Design, Jan. 2002.
Oct. 5, 2001
Agrawal, Kim and Saluja
21
Thank you
Oct. 5, 2001
Agrawal, Kim and Saluja
22