HIGH-SPEED VLSI TESTING WITH
SLOW TEST EQUIPMENT
 Available automatic test equipment (ATE) speed is 100200MHz; VLSI chip speed is 0.5-1GHz.
 Expensive to replace the existing ATE. Besides, chip
speed remains an advancing target.
 Existing delay test solutions insert hardware into chip
• Scan method has limited path activation capability
• Built-in self-test (BIST) uses random vectors that often
activate non-functional paths
 Problem: Develop a delay test method for slow ATEs that
will give similar path coverage as obtained with an atspeed ATE
• Add no test hardware to chip
• Test only functional paths
June 10, 2001
High-speed test
1
A NEW METHOD
 Given a vector-set with specific at-speed PDF coverage,
the ATE repeats the slow-speed test N times, where N is
the ratio of chip-speed to the ATE-speed.
 In each slow-speed vector application
• Flip-flops are clocked at the rated high-speed
• Output monitoring instant is advanced by an additional
interval that equals rated high-speed clock period
 Test application time = N
Slow vector
application, N=4
Vector i
i+1
x (test time of at-speed ATE)
Slow output monitoring
repeated N times
PI
CK
Rated-clock generated
by pin-multiplexing
June 10, 2001
2
Sequential
circuit
under test
(gates and
flip-flops)
PO
Appln. 1
Appln. 2
Appln. 3
Appln. 4
High-speed test
2
SOME RESULTS OF NEW METHOD
1. Simulated Benchmark circuits (ISCAS’89)
Path delay fault
Coverage (%)
50
40
At-speed
ATE
S510 : 5,000 random vectors
S5378 : 5,000 random vectors
Slow ATE
Slow ATE
(N=2, 3, 4)
gives the same
path coverage
as at-speed ATE
(N=1).
30
20
10
1
2
3
4
ATE slowdown factor (N)
2. A 4MHz off-the-shelf chip tested on Agilent 82000 ATE
N=1 (at-speed) N=2 (Half-speed) N=4 (1/4 speed)
4.367 MHz
3.937
3.922
MHz* than those tested
MHz*by at-speed test.
* Some tested paths are longer
June 10, 2001
High-sped test
3