Mutiple Faults: Modeling,
Simulation and Test
Yong C. Kim
University of Wisconsin, Dept. of ECE, Madison, WI 53706, USA
kimy@ece.wisc.edu
Vishwani D. Agrawal
Agere Systems, Murray Hill, NJ 07974, USA
va@agere.com
Kewal K. Saluja
University of Wisconsin, Dept. of ECE, Madison, WI 53706, USA
saluja@engr.wisc.edu
Jan. 11, '02
Kim, et al., VLSI Design'02
1
Problem Statement

ATPG targets single stuck-at faults:
 Efficient simulation and ATPG programs are available
for single faults.

Some applications require a limited capability to
selectively target multiple faults:
 Combinational ATPG for partial scan; Kim, et al., VLSI
Design’01, ITC’02.
 Fault diagnosis.
 Circuit optimization by redundancy removal.
 Bridging faults.
 Problem: To find a test for a multiple stuck-at
fault using a single-fault ATPG procedure.
Jan. 11, '02
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Talk Outline



Background
A single fault model for multiple faults
Applications
 Combinational ATPG for acyclic sequential circuits
 Exclusive test for diagnosis

Conclusion
 Other applications
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Background


Number of multiple stuck-at faults in a k line
circuit is 3k-1.
Single-fault tests are found to cover most
multiple faults:
 Agarwal and Fung, IEEETC’81
 Hughes and McCluskey, ITC’86
 Jacob and Biswas, ITC’88

Multiple-fault ATPG algorithms are not faultoriented:
 Bossen and Hong, IEEETC’71
 Kohavi and Kohavi, IEEETC’72
 Aboulhamid, et al., JETTA’93
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Kim, et al., VLSI Design'02
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An Obvious Fault Model
a
b
c
s-a-1
s-a-0
s-a-0
New PI
fixed at 0
A
s-a-1
a
A
b
B
c
C
B
C
 Fault is always active in the model even when it is not

activated, e.g., a=1, b=0, c=0.
Some simulators and ATPG programs may not properly
handle fixed logic signals.
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A New Single Fault Model

Insert a two-input in-line gate in each faulty line:

Insert an AND gate with output s-a-1 fault
 AND for s-a-0 fault
 OR for s-a1 fault
s-a-1
a
b
c
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s-a-1
s-a-0
s-a-0
A
a
A
b
B
c
C
B
C
Kim, et al., VLSI Design'02
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Proof of Correctness

Fault-free circuit:
 A=a+abc=a
 B=b(a+b+c)=b
 C=c(a+b+c)=c
a
A
b
B
c
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C
a
A
b
B
c
C
Kim, et al., VLSI Design'02
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Proof of Correctness

Faulty circuit:
 A=a+1=1
 B=b.0=0
 C=c.0=0
s-a-1
a
b
c
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s-a-1
s-a-0
s-a-0
A
a
A
b
B
c
C
B
C
Kim, et al., VLSI Design'02
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Size of Model

Model of a multiple fault of multiplicity n
requires at most n+3 modeling gates.
s-a-1
a
b
c
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s-a-1
s-a-0
s-a-0
A
a
A
b
B
c
C
B
C
Kim, et al., VLSI Design'02
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Comb. ATPG for Seq. Circuits

Single-fault tests for acyclic sequential circuits
can be obtained by combinational ATPG.
 Kim, et al., VLSI Design’01, ITC’01.
 A combinational model is made for the sequential
circuit.
 About 83% of sequential circuit faults map onto single
faults in the combinational model.
 On an average about 17% of sequential circuit faults
map onto multiple faults in the combinational model.
 The method allows 100% fault efficiency.
 General sequential circuits can be made acyclic
by partial scan; Cheng and Agrawal, IEEETC’90.
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An Example
Unbalanced nodes
a
s-a-0
s-a-0
b
FF
Combinational
vector
a1
0
b1
X
Balanced
model
s-a-0
dseq =
1
Single fault
1 s-a-0
0
1/0
Multiple fault
a0
b0
1
s-a-0
1/0
1
1/0
FF replaced
by buffer
Test sequence: 11, 0X
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Acyclic Partial-Scan ISCAS’89
Circuits:
Circuit Total Scan Mult. Flts. Max Model Size
name FFs FFs
%
depth PI Gate
s5378
179
30
52.1
19 3.21 6.50
s9234
228 152
9.2
4 1.40 2.14
s13207
669 310
31.1
22 2.08 3.32
s15850
597 441
52.4
29 3.27 6.98
s35932 1728 306
13.1
34 2.33 3.80
s38417 1638 1080
4.3
9 1.13 1.64
s38584 1425 1115
18.9
35 2.32 4.13
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MF
%
2.1
4.2
1.5
1.4
1.4
1.1
0.3
12
Acyclic Partial-Scan ISCAS’89
Circuits: Test Generation
Circuit Sequential ATPG* Combinational ATPG
Name FC
FE TGT(s) FC
FE
TGT(s)
s5378
s9234
s13207
s15850
s35932
s38417
93.69 99.71 1268.0 93.69 99.71
93.16 99.94 426.0 93.16 99.94
97.13 99.97 1008.0 97.13 99.97
96.65 99.97 856.0 96.66 99.97
89.80 100.00 569.0 89.80 100.00
99.25 99.54 861.0 99.25 99.55
23.3
85.7
55.0
140.8
79.4
98.2
FC: cov. (%), FE: efficiency (%), TGT: CPU s Sun Ultra 10
*Gentest for seq. and TetraMAX for comb. ATPG
(Hitec produced equivalent FC, FE and TGT within 10% of Gentest)
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Exclusive Test


Given two faults, an exclusive test detects one
fault but does not detect the other.
A test for the multiple fault (f1,f2) in the following
circuit is an exclusive test for f1 and f2 in CUT.
Exclusive
test
vector
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CUT
with f1
0/1 or 1/0
CUT
with f2
Kim, et al., VLSI Design'02
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Diagnostic Test Example
a
Fault
g
d
b
c
e
f
100% coverage
Tests:
a 00011
b 01100
c 10101
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i
s-a-1
s-a-1
h
a1
b1
c0
c1
d1
f1
g0
h0
i0
i1
Kim, et al., VLSI Design'02
Test
Diagnostic
syndrome number
10100
5
00010
8
00101
20
01010
10
00010
8
00100
4
00001
16
01000
2
01001
18
10110
13
15
Exclusive Test for b1 and d1
a 0
b 0
c 0
g
d
CUT
with b1
i
e
f
h
0/1
s-a-1
g
d
i
e
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f
Kim, et al., VLSI Design'02
h
CUT
with d1
16
Diagnosis With Exclusive Test
a
Fault
g
d
b
c
i
s-a-1
s-a-1
e
f
h
100% coverage
tests and excl. test:
a 000110
b 011000
c 101010
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a1
b1
c0
c1
d1
f1
g0
h0
i0
i1
Kim, et al., VLSI Design'02
Test
Diagnostic
syndrome number
101000
5
000101
40
001010
20
010100
10
000100
8
001000
4
000010
16
010000
2
010010
18
101101
45
17
Conclusion


Single fault model allows effective use of
existing single-fault ATPG and simulation tools
to handle multiple fault.
Applications include:
 Combinational ATPG for sequential circuits
 Circuit optimization by removing multiple fault
redundancies (see this paper)
 Improving diagnostics by exclusive tests
 Other types of tests like antitest and concurrent test
(unpublished)
 The modeling technique is useful for non-stuck
type of faults that map onto multiple stuck-at
faults, e.g., bridging faults (see this paper).
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