Exclusive Test and its
Application to Fault
Diagnosis
Vishwani D. Agrawal
Dong Hyun Baik
Yong C. Kim
Kewal K. Saluja
Overview
► Problem Statement
► Introduction
 Background on Diagnosis
 Definitions for Diagnosis
► Main




Idea
Exclusive Test
Example of Exclusive Test
Exclusive Test Generation
Properties of Exclusive Test
► Diagnosis Method
► Results
► Conclusion
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
2
Problem Statement
► Obtain
high resolution diagnostic
test using a single-fault ATPG.
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
3
Introduction: Background on Diagnosis
► Single-fault
dictionary approaches
 Simulation based: Chang et al.
Fault Diagnosis of Digital Systems, NY, Wiley-Interscience,
1970
 Most common method for diagnosis
► Diagnostic test pattern generation: Specialized ATPGs
 Implication based: Gruning et al.
DIATEST: A Fast Diagnostic Test Pattern Generator for
Combinational circuits - ICCAD, 1991
 Multiple-pass strategy: Savir et al. Testing for, and Distinguishing between Failures - FTCS,
1982
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
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Introduction: Definitions for Diagnosis
►
Consider CUT on the right
 All 10 faults are detected by 5
test vectors: T1 = 001, T2 = 010,
T3 = 011, T4 = 101, T5 = 111
 Diagnostic dictionary
a
g
d
b
T1T2T3T4T5 T6
a1
10100
0
b1
00010
1
c0
00101
0
c1
01010
0
d1
00010
0
f1
00100
0
g0
00001
0
h0
01000
0
i0
01001
0
i1
10110
1
c
i
s-a-1
s-a-1
e
Add T6 = 000
f
h
● DR = 10/9=1.11
• Diagnostic
Resolution
(DR)
.
►
10
Faults,
but
only
9
● DR = 10/10=1.00
syndromes:
 DR = No. of faults (classes)
► 10 syndromes:
b1 and d1 cannot
be
of syndromes
b1distingushied
and d1 areNo.
now
distinguished
test syndrome for
fault g0
 A measure of quality of
diagnosis
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
5
Main Idea
► Exclusive
test
 An Input vector that detects only one fault from
a pair of targeted faults at a primary output
C0  C1   C0  C2   1
C1  C2  1
 C0:
A fault free circuit
 C1: CUT with fault f1
 C2: CUT with fault f2
Exclusive
test vector
CUT
fault f1
D
CUT
fault f2
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
6
Example of Exclusive Test
►
Application
 Generate an additional vector to improve diagnostic resolution:
distinguish a pair of faults, b1 and d1.
►
Example
 Diagnostic dictionary
a
T1T2T3T4T5 T6
a1
10100 0
b1
00010 1
c0
00101 0
c1
01010 0
d1
00010 0
f1
00100 0
g0
00001 0
h0
01000 0
i0
01001 0
i1
10110 1
g
d
b
c
e
Exclusive
test vector
“abc”
T6 = 000
i
s-a-1
s-a-1
f
CUT
fault b1
CUT
fault d1
h
D
Exclusive Test Generation
Kim, Agrawal and Saluja “Multiple Faults: Modeling, Simulation and test” VLD 2002
0 a
Exclusive test for (b1,d1), T6 = 000
g
d
0b
i
b1
e
d
f
D
s-a-1
0 c
h
g
d1
i
h
e
f
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
8
Properties of Exclusive Test
► If
there exists an exclusive test two
faults then they can be distinguished
from each other by using that test.
► If no exclusive test exists then the faults
cannot be distinguished; two faults form
an equivalent fault set.
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
9
Diagnosis Method
Start with fault detection tests
Make dictionary and isolate
undiagnosed fault sets
Done
Yes
Is DR satisfactory?
No
Generate an exclusive test for an
undiagnosed fault pair
Append the test
Yes
Test exists?
No
Form an equiv.
Fault set
ATPG aborted
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
10
Results: Model
► For
illustration, an XOR-tree is added to
the output of the circuit under test to
make it a single output circuit.
 We use * to denote a modified circuit with
a single output XOR-tree at its outputs.
► General
later.
multiple-PO case is discussed
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
11
Test Generation−ISCAS85 Circuits
Circuit names
c432* c880*
# of fault detection tests
c1908*
c3540*
82
104
176
239
524
942
1879
3428
# of redundant faults
4
5
4
90
# of aborted faults
0
2
27
81
520
935
1848
3257
Fault coverage (%)
99.24 99.26
98.35
95.01
Fault efficiency (%)
100 99.79
98.56
97.57
# of equiv. collapsed faults
# of detected faults
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
12
Diagnostic Results−ISCAS85 Circuits
Circuit names
c432*
c880*
c1908*
c3540*
# of faults
520
935
1848
3257
# of syndromes
426
789
1450
2706
# of diagnosed faults
354
686
1121
2351
Diagnostic resolution ( DR)
1.22
1.19
1.27
1.20
5
6
8
12
82
104
176
239
# of syndromes
506
870
1579
2844
# of diagnosed faults
492
808
1331
2559
Diagnostic resolution (DR)
1.03
1.07
1.17
1.14
2
3
8
8
126
152
262
328
44
48
86
89
0
0
0
1
14
79
321
662
Max. faults per syndrome
# of fault detection vectors
Max. faults per syndrome
Total test vectors
# of exclusive tests added
# of equivalent pairs
# of aborted pairs
Test Generation−c432
Detection tests
c432*
c432
c432
82
82
82
524
524
524
# of redundant faults
4
4
4
# of aborted faults
0
0
0
# of detected faults
520
520
520
Fault coverage (%)
99.24
99.24
99.24
Fault efficiency (%)
100
100
100
# of fault detection tests
# of equiv. collapsed faults
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
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Diagnostic Results−c432
Circuit names
c432*
c432
c432
# of faults
520
520
520
# of syndromes
428
495
500
# of diagnosed faults
354
471
479
Diagnostic resolution (DR)
1.22
1.05
1.04
5
5
4
# of fault sets
506
507
507
# of syndromes
506
507
507
# of diagnosed faults
492
494
494
Diagnostic resolution (DR)
1.00
1.00
1.00
1
1
1
131
131
123
# of exclusive tests
49
13
41
# of equivalent pairs
14
13
13
Max. faults per syndrome
Max. faults per syndrome
Total test vectors
# of aborted pairs
0
0
0
C432: Simulated using tests derived with c432*, then targeted only undiagnosed faults
Conclusion
► Definition
of an exclusive test and an ATPG
method are introduced.
► A comprehensive exclusive test based
diagnostic method is presented where a
conventional single fault ATPG can be used.
► Results for ISAS85 benchmark circuits are
presented.
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
16
Supplement 1:
► Kim,
Multiple Fault Model
Agrawal and Saluja -
 “Multiple Faults: Modeling, Simulation and test” - VLSI
Design,2002
 Convert multiple fault test generation problem into single
fault test generation problem.
s-a-1
s-a-1
a
A
a
A
B
b
B
C
c
C
D
d
D
s-a-1
b
c
d
s-a-0
s-a-0
Multiple (4) stuck-at fault
Equivalent Single Stuck-at fault
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
18
Supplement 2: Test Generation−ISCAS85 Circuits
Circuit names
# of detection tests
c17*
c432*
c499*
c880*
c1355*
c1908*
c2670*
c3540*
6
82
58
104
104
176
236
239
22
524
758
942
1574
1879
2747
3428
# of redundant faults
0
4
0
5
0
4
84
90
# of aborted faults
0
0
32
2
32
27
884
81
# of detected faults
22
520
726
935
1542
1848
1779
3257
Fault coverage (%)
100
99.24
95.78
99.26
97.97
98.35
64.76
95.01
Fault efficiency (%)
100
100
95.78
99.79
97.97
98.56
66.8
97.57
# of equiv. faults
Agrawal, Baik, Kim and Saluja: VLSI Design 2003
19
Supplement 3: Diagnostic Results−ISCAS85 Circuits
Circuit names
c17*
c432* c499*
c880*
c1355* c1908*
c2670*
c3540*
# of faults
22
520
726
935
1542
1848
1779
3257
# of syndromes
14
426
691
789
873
1450
1285
2706
9
354
661
686
360
1121
972
2351
1.57
1.22
1.05
1.19
1.77
1.27
1.38
1.2
4
5
4
6
11
8
11
12
# of diagnosed faults
DR
Max. faults per syndrome
Diagnosis with detection and exclusive tests
# of faults
22
520
726
935
1542
1848
1779
3256
# of syndromes
22
506
710
870
902
1579
1385
2844
# of diagnosed faults
22
492
694
808
366
1331
1097
2559
DR
1
1.03
1.02
1.07
1.71
1.17
1.28
1.14
Max. faults per syndrome
1
2
2
3
3
8
11
8
11
126
72
152
129
262
293
328
# of exclusive tests
5
44
14
48
25
86
57
89
# of equivalent pairs
0
0
0
0
0
0
0
1
# of aborted pairs
0
14
16
79
744
321
630
662
Total test vectors