Spectral RTL Test Generation
for Gate-Level Stuck-at Faults
Nitin Yogi and Vishwani D. Agrawal
Auburn University, Department of ECE,
Auburn, AL 36849, USA
Nov. 21, 2006
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Outline
Need for High Level Testing
 Problem and Approach
 Spectral analysis and test generation
 RTL testing approach
 Experimental Results
 Conclusion

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Need for High Level Testing
 Motivations
Reduced
for high level testing:
test generation complexity
 Reduced
time and cost for test development
Early
resolution of testability issues
Difficulty of gate-level test generation for
black box cores with known functionality
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Problem and Approach

The problem is …
 Develop

an effective RTL ATPG method
And our approach is:
 Implementation-independent


characterization:
RTL test generation
Spectral analysis of RTL vectors
 Test
generated to cover faults in gate-level
implementation:


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Generation of spectral vectors
Fault simulation and vector compaction
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Faults Modeled for an RTL Module
Inputs
Combinational
Logic
RTL
stuck-at
fault
sites
Outputs
FF
FF
A circuit is an interconnect of several RTL modules.
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Spectral Characterization of a Digital Bit-Stream
w0
• Walsh functions: a complete
orthogonal set of basis functions that can
represent any arbitrary bit-stream.
Walsh functions (order 8)
w1
• Walsh functions form the rows of a
Hadamard matrix.
w2
w3
H8 = 1 1 1 1 1 1 1 1
1 -1 1 -1 1 -1 1 -1
1 1 -1 -1 1 1 -1 -1
1 -1 -1 1 1 -1 -1 1
1 1 1 1 -1 -1 -1 -1
1 -1 1 -1 -1 1 -1 1
1 1 -1 -1 -1 -1 1 1
1 -1 -1 1 -1 1 1 -1
w4
w5
w6
w7
time
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Example of Hadamard matrix
of order 8
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Walsh Coefficients of a Bit-Stream

A bit-stream is correlated with each row of Hadamard matrix.

Highly correlated basis functions => retained as essential components
Others => noise.
Bit stream
to analyze
Correlating with Walsh functions by
multiplying with Hadamard matrix.
Hadamard Matrix
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Bit
stream
Spectral
coeffs.
Essential component
(others noise)
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Bit-Stream Generation


Original spectrum

New spectrums are generated retaining essential components and adding
random noise.
New spectrums are converted into bit-streams by multiplying with
Hadamard matrix.
Any number of bit-streams can be generated;
All contain the same essential components but differ in noise
Perturbation
New spectrum
multiplying with
Hadamard matrix
Essential
component
retained
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Bits changed
New bit-stream
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RTL Testing Approach
(Circuit Characterization)

RTL test generation:
 Test
vectors generated for RTL faults
(PIs, POs and inputs - outputs of RTL modules and
flip-flops.)

Spectral analysis:
 Test
sequences for each input bit-stream are analyzed
using Hadamard matrix.
 Amount of perturbation is determined by a gradually
increasing noise level.
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Power Spectrum: “Interrupt” Signal
Normalized Power
Essential
components
Noise
components
Spectral Coefficients
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PARWAN
Processor
Circuit
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Random
level
(1/128)
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Power Spectrum: “Ready” Signal
Normalized Power
Examples of
Essential
components
PARWAN
Processor
Circuit
Examples of
Noise
components
Random
level
(1/128)
Spectral Coefficients
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Power Spectrum: “DataIn[5]” Signal
PARWAN
Processor
Circuit
Normalized Power
Examples of
Essential
components
Examples of
Noise
components
Random
level
(1/128)
Spectral Coefficients
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Normalized Power
Power Spectrum: A Random Signal
Average
level
(1/128)
Spectral Coefficients
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Selecting Minimal Vector Sequences Using ILP

Fault simulation of new sequences



A set of perturbation vector sequences {V1, V2, .. , VM} are generated.
Vector sequences are fault simulated and faults detected by each is
obtained.
Compaction problem



Find minimum set of vector sequences which cover all the detected
faults.
Minimize Count{V1, … ,VM} to obtain compressed seq. {V1,… ,VC}
where {V1, … ,VC}  {V1, … , VM}
Fault Coverage{V1, … ,VC} = Fault Coverage{V1, … ,VM}
Compaction problem is formulated as an Integer Linear Program
(ILP) [1].
[1] P. Drineas and Y. Makris, “Independent Test Sequence Compaction
through Integer Programming," Proc. ICCD’03, pp. 380-386.
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Results: Circuit Characteristics




RTL Spectral ATPG technique applied to the following benchmarks:
 4 ITC’99 high level RTL circuits
 4 ISCAS’89 circuits.
 PARWAN processor (Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.)
Characteristics of benchmark circuits:
Circuit
benchmark
PIs
POs
FFs
b01
ITC’99
2
2
5
b09
ITC’99
1
1
28
b11
ITC’99
7
6
31
b14
ITC’99
34
54
239
s1488
ISCAS’89
8
19
6
s5378
ISCAS’89
36
49
179
s9234
ISCAS’89
37
39
211
s35932
ISCAS’89
36
320
1728
PARWAN
processor
11
23
53
ATPG for RTL faults and fault simulation performed using commercial sequential ATPG tool
Mentor Graphics FlexTest.
Results obtained on Sun Ultra 5 machines with 256MB RAM .
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Results for b11-A**
RTL characterization:
No. of RTL
faults
Number of
Vectors
RTL test cov.
(%)
CPU*
seconds
No. of spec.
components
Gate level
test cov. (%)
240
224
76.16
530
256
74.09
RTL-ATPG results:
No. of
gate-level
faults
2380
RTL ATPG
Spectral Test Sets
Gate level
cov. (%)
Number of
vectors
CPU*
seconds
Gate level
cov. (%)
Number of
vectors
CPU*
seconds
88.84
768
737
84.62
468
1866
* Sun Ultra 5, 256MB RAM
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FlexTest Gate-level ATPG
** Area-optimized synthesis in Mentor’s Leonardo
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b11-A Circuit
100
90
Test Coverage (%)
80
RTL spectral
ATPG
70
60
Gate-level
ATPG
50
Random
vectors
40
30
RTL fault
vectors
20
10
0
1
10
100
1000
10000
Number of Vectors
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PARWAN processor
100
90
Test coverage (%)
80
RTL spectral
ATPG
70
60
Gate-level
ATPG
50
Random
vectors
40
30
RTL fault
vectors
20
10
0
1
10
100
1000
10000
No. of Vectors
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Results
Circuit
name
No. of
gatelevel
faults
b01-A
RTL-ATPG spectral tests
FlexTest Gate-level ATPG
Random inputs
Cov.
(%)
No. of
vectors
CPU
(secs)
Cov.
(%)
No. of
vectors
CPU
(secs)
No. of
vectors
Cov
(%)
228
99.57
128
19
99.77
75
1
640
97.78
b01-D
290
98.77
128
19
99.77
91
1
640
95.80
b09-A
882
84.68
640
730
84.56
436
384
3840
11.71
b09-D
1048
84.21
768
815
78.82
555
575
7680
6.09
b11-A
2380
88.84
768
737
84.62
468
1866
3840
45.29
b11-D
3070
89.25
1024
987
86.16
365
3076
3840
41.42
b14
25894
85.09
6656
5436
68.78
500
6574
12800
74.61
s1488
4184
95.65
512
103
98.42
470
131
1600
67.47
s5378
15584
76.49
2432
2088
76.79
835
4439
3840
67.10
s5378*
15944
73.59
1399
718
73.31
332
22567
2880
62.77
s9234
28976
17.36
64
721
20.14
6967
18241
160
15.44
s9234*
29400
49.47
832
2734
48.74
12365
4119
2176
33.06
s35932
103204
95.70
256
1801
95.99
744
3192
320
50.70
PARWAN
5380
89.11
1344
1006
87.11
718
3626
6400
76.63
* Reset input added.
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Conclusion





Spectral RTL ATPG technique applied to ITC’99 and
ISCAS’89 benchmarks, and a processor circuit.
Vectors generated for RTL faults were spectrally
analyzed and new vectors generated through
perturbation.
In most cases, Spectral RTL ATPG gave similar or better
test coverage in shorter CPU time as compared to
sequential ATPG
Test generation using Spectral RTL ATPG brings with it
the benefits of high level testing
Techniques that will enhance Spectral ATPG are:



Efficient RTL ATPG
Accurate determination and use of noise components
Better compaction algorithms
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Thank You !
Questions ?
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