Upper Bounding Fault Coverage
in Stafan
Vishwani D. Agrawal
Auburn University, Dept. of ECE, Auburn, AL 36849
Soumitra Bose
Vijay Gangaram
Intel Corporation, Design Technology, Folsom, CA 95630
Presented at 24th IEEE VLSI Test Symposium, April-May 2006
See full paper at:
http://www.eng.auburn.edu/~vagrawal/TALKS/vts06_bose.pdf
9/13/2006
VLSI D&T Seminar, Fall 06
1
Outline
• Problem statement and motivation
• Background
• Upper bounding algorithm
• Benchmark results
• An application: test-point insertion
• Conclusion
9/13/2006
VLSI D&T Seminar, Fall 06
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Problem Statement and Motivation
• A fault simulation problem
• Large non-scan or partial-scan circuits
• Long functional verification vector sequences
• Objective:
– Find compact high fault coverage vectors for testing
– Find test points for DFT
• Motivation
• Exact fault simulation is too expensive
• Statistical fault simulator is a useful tool, but needs
accuracy
– In coverage estimation
– In identifying faults not detectable by vector sequence
9/13/2006
VLSI D&T Seminar, Fall 06
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Background
• Approximate fault simulation
– Per-vector analysis
• Critical path tracing (CPT), Abramovici et al., IEEE D&T
1984.
• Necessary conditions, Akers et al., ITC 1990.
– Post-simulation analysis, Stafan, Jain and Agrawal,
IEEE-D&T 1985.
• Dominator analysis in ATPG, Kirkland and Mercer, ITC
1987.
Dominator
Fanout
stem
Fault detection at fanout stem depends on signal states
in this part and the observability of the dominator.
9/13/2006
VLSI D&T Seminar, Fall 06
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Stafan: A Tutorial Example
Incorrectly
detected
faults
sa0
11001 sa1
C0=0.4
C1=0.6
OB0=1.0
OB1=1.0
OB0=1.0, OB1=0.0 (observabilities)
C0=0.4, C1=0.6 (controllabilities)
S=0.4 (sensitization count)
sa1 11001
sa1
C0=0.4
C1=0.6
S=1.0
OB0=0.0
OB1=1.0
00110
C0=0.6, C1=0.4
S=0.6
OB0=1.0, OB1=0.0
Detected
fault
00000
sa1
C0=1.0
C1=0.0
OB0=1.0
OB1=1.0
PD: Prob(sa0 detected) = C1 × OB1, Prob(sa1 detected) = C0 × OB0
Threshold detection by N vectors: 1 – (1 – PD)N ≥ 0.5
9/13/2006
VLSI D&T Seminar, Fall 06
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A Circuit Requiring Dynamic Analysis
Vector-less static analysis can identify redundant stem faults
in the previous example.
Stem requires
vector-specific
analysis
Dominator
When only 00 and 11 patterns occur on these lines,
the stem will be unobservable
9/13/2006
VLSI D&T Seminar, Fall 06
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Upper Bounding Algorithm
• Structural Analysis
• For each fanout stem identify dominator set (gates on
paths between the stem and its dominator)
• Based on the inversion parities of paths in the dominator
set determine stem observability conditions
• Monitor Ocurrence of Selected Signal States During
Logic Simulation
• For a gate, set of input states that forbids path
sensitization
• For a fanout stem with all same parity paths, set of offpath signal states that forbids sensitizstion of any path
• For a fanout stem with different parity paths, set of offpath signal state that simultaneously sensitizes diffrenet
parity paths
• Similar conditions derived for mixed parity paths
• Total number of conditions: O(2×k×N), k = average
fanin of gates, N = number of gates
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VLSI D&T Seminar, Fall 06
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Algorithm: Fanout Reconvergence (I)
Portion of c17: Fanout G1
reconverges with same
inversion parity at G5.
Same vector applied twice:
11
G2
00
11
11
G1
00
00
sa0
11
G5
sa1
G3
11
Detected faults not detected by stafan
Negative errors: G1 output found unobservable.
Structural analysis: Stem G1 has two {G2 and G3} same parity paths.
Signal monitoring: Only pattern 0XX0 can make stem G1 unobservable
 G1 is observable.
9/13/2006
VLSI D&T Seminar, Fall 06
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Algorithm: Fanout Reconvergence (II)
Undetected fault detected by stafan
I1
10
G0
sa0
Portion of c17: Fanout I2
reconverges with different
inversion parities at G4.
01
G4
I2
10
11
I4
I3
11
10
11
G1
00
G2
Positive error: When observable fanouts of I2 are treated as independent.
Structural analysis: Fanouts paths {G0, and G1-G2} have different parities.
Signal monitoring: Propagation through G0: {I1=1 and (I3=0 or I4=0)} = false
Propagation through G1-G2: {(I3=1 and I4=1) and I1=0} = false
 I2 is unobservable
9/13/2006
VLSI D&T Seminar, Fall 06
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Results: Benchmark Circuits
Exact
Stafan*
UB Stafan
c432
93.15
94.85
93.32
CPU % over
logic
simulation
33.3
c880
91.08
90.02
92.04
20.0
c1355
87.93
18.74
88.82
22.2
c1908
69.79
75.71
73.10
30.8
c2670
77.28
63.49
78.56
36.8
c3540
70.79
76.26
71.99
30.8
c5315
91.74
76.59
93.64
34.9
c6288
99.74
92.91
99.74
16.4
c7552
84.47
74.54
87.99
52.2
Fault coverage (%)
Circuit
* Original stafan; different from “vanilla estimate” in the paper,
which is an improved stafan.
9/13/2006
VLSI D&T Seminar, Fall 06
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Fault Coverage of c2670
Error in upper bound estimate varies with coverage:
90
80
70
coverage (%)
60
50
exact
40
stafan
30
UB
20
UB-exact
10
0
1
5
9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97
vectors
Peak error of about 12% after 8 vectors and 53% coverage.
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VLSI D&T Seminar, Fall 06
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Application: Scanout Selection
•
Given large functional sets, each with ~106 vectors:
1. low individual vector set coverage
2. high cumulative coverage
3. set of potential observation (scanout) points
find minimal observation points that maximize coverage.
•
Exact solution: fault simulation with no fault dropping.
•
Conventional fault simulation takes several days.
•
Estimate fault detection status for every fault at every
potential observation point.
•
Find a minimal subset of candidates that covers all faults.
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VLSI D&T Seminar, Fall 06
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Application: Scanout Selection
Circuit characteristics
Name
No. of Vector
Gates
sets
Total
Flipflops
Scanout flip-flop selction
Max.
cov.
(%)
d1
130k
220
14,540 77.6
d2
180k
45
8,500
d3
494k
112
12,550 78.5
88.9
No. of
By fault sim.
By UB-stafan
flipflops
CPU
Cov.
Cov.
time
%
CPU
time
2,000
8days
72.7
45min
74.1
200
12days
81.4
1.5hrs
85.7
1,600 15days
74.0
4hrs
76.8
Scan
%
Note: Fault simulation runtimes assume fault dropping.
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VLSI D&T Seminar, Fall 06
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Conclusion
• Estimation errors due to reconverging fanouts:
– Positive: Undetected faults estimated as detected.
– Negative: Detected faults estimated as undetected.
• Upper Bounding improvements:
– Positive errors reduced by dominators and monitoring
– Negative errors reduced by reconvergence analysis
– Useful for
• Test development
• DFT – test point selection
• Structural analysis of dominators and signal monitoring can
reduce fault detection errors for non-random functional
input sequences; to be discussed in a forthcoming paper.
9/13/2006
VLSI D&T Seminar, Fall 06
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ITC’06: Improved Stafan – Average, and
Upper/Lower Bound Estimates
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VLSI D&T Seminar, Fall 06
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