CSV881: Low-Power Design
Power Dissipation in CMOS Circuits
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
1
nMOS Logic (Inverters)
For logic 1 input,
continuous static
power is dissipated.
Pseudo-nMOS
Saturated-load nMOS
R. C. Jaeger and T. N. Blalock, Microelctronic Circuit Design,
Third Edition, McGraw-Hill, 2006, Chapter 6.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
2
CMOS Logic (Inverter)
VDD
No current flows
from power supply!
Where is power
consumed?
GND
F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect
Metal-Oxide-Semiconductor Triodes,” IEEE International SolidState Circuits Conference Digest, vol. IV, February 1963, pp.
32-33.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
3
Components of Power

Dynamic

Signal transitions
 Logic
activity
 Glitches


Short-circuit (small)
Static

Leakage
Copyright Agrawal, 2011
Ptotal =
=
Lectures 3, 4: CMOS Circuits
Pdyn + Pstat
Ptran + Psc + Pstat
4
Power of a Transition: Ptran
V = VDD
R = Ron
i(t)
vi (t)
Large
resistance
v(t)
C = CL
Ground
C
=
Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
5
Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
Copyright Agrawal, 2011
=
dq(t)/dt
Lectures 3, 4: CMOS Circuits
6
C dv(t)/dt =
[V – v(t)] /R
dv(t)
V – v(t)
───
=
─────
dt
RC
dv(t)
dt
∫ ───── = ∫ ────
V – v(t)
RC
–t
ln [V – v(t)]
=
── + A
RC
i(t)
=
Initial condition, t = 0, v(t) = 0 → A = ln V
–t
v(t) =
V [1 – exp(───)]
RC
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
7
v(t) =
i(t)
Copyright Agrawal, 2011
=
–t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
Lectures 3, 4: CMOS Circuits
V
–t
── exp( ── )
R
RC
8
Total Energy Per Charging
Transition from Power Supply
Etrans =
=
Copyright Agrawal, 2011
∞
∫ V i(t) dt =
0
CV
∞V
2
–t
∫ ── exp( ── ) dt
0 R
RC
2
Lectures 3, 4: CMOS Circuits
9
Energy Dissipated per Transition in
Resistance
∞2
R ∫ i (t) dt
0
Copyright Agrawal, 2011
=
V ∞
– 2t
R ──
∫
exp(
──
)
dt
R2 0
RC
=
1
2
─ CV
2
2
Lectures 3, 4: CMOS Circuits
10
Energy Stored in Charged Capacitor
∞
∞
–t V
–t
∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
2
= ─ CV
2
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
11
Transition Power

Gate output rising transition
2
Energy dissipated in pMOS transistor = CV /2
2
 Energy stored in capacitor = CV /2


Gate output falling transition

2
Energy dissipated in nMOS transistor = CV /2
2
Energy dissipated per transition = CV /2
 Power dissipation:
2
Ptrans =
Etrans α fck =
α fck CV /2
α =
activity factor
fck =
clock frequency

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
12
Components of Power

Dynamic

Signal transitions
0
activity
 Glitches

Short-circuit
Static

Leakage
Copyright Agrawal, 2011
2
Delay
=1
 Logic

GLITCH
Delay=2
1
3
0
Ptotal =
=
Lectures 3, 4: CMOS Circuits
Pdyn + Pstat
Ptran + Psc + Pstat
13
Short Circuit Power of a Transition: Psc
VDD
vi (t)
isc(t)
vo(t)
CL
Ground
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
14
Short Circuit Current, isc (t)
VDD
VDD - VTp
Vi (t)
Volt
p-transistor
starts
conducting
n-transistor
cuts-off
Vo(t)
VTn
0
Iscmaxf
isc(t)
Isc
0
Copyright Agrawal, 2011
tB
tE
Lectures 3, 4: CMOS Circuits
1
Time (ns)
15
Peak Short Circuit Current
Increases with the size (or gain, β) of
transistors
 Decreases with load capacitance, CL
 Largest when CL = 0
 Reference: M. A. Ortega and J. Figueras,
“Short Circuit Power Modeling in
Submicron CMOS,” PATMOS ’96, Aug.
1996, pp. 147-166.

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
16
Short-Circuit Energy per Transition

Escf =
=
tE
∫tB
VDD isc(t)dt
(tE – tB) Iscmaxf VDD / 2

Escf =
tf (VDD - |VTp| - VTn) Iscmaxf / 2

Escr =
tr (VDD - |VTp| - VTn) Iscmaxr / 2

Escf = Escr = 0, when VDD = |VTp| + VTn
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
17
Short-Circuit Power
Increases with rise and fall times of input.
 Decreases for larger output load
capacitance; large capacitor takes most of
the current.
 Small, about 5-10% of dynamic power;
momentary shorting of supply and ground
during opening and closing of transistor
switches.

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
18
Short-Circuit Power Calculation
Assume equal rise and fall times
 Model input-output capacitive coupling
(Miller capacitance)
 Use a spice model for transistors


T. Sakurai and A. Newton, “Alpha-power Law
MOSFET model and Its Application to a
CMOS Inverter,” IEEE J. Solid State Circuits,
vol. 25, April 1990, pp. 584-594.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
19
Short Circuit Power
Psc =
Copyright Agrawal, 2011
α fck Esc
Lectures 3, 4: CMOS Circuits
20
Psc, Rise Time and Capacitance
VDD
Ron
vi (t)
tf
VDD
ic(t)+isc(t)
vo(t)
CL
R = large
vo(t)
tr
Ground
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
vo(t)
───
R↑
21
isc, Rise Time and Capacitance
Isc(t) =
Copyright Agrawal, 2011
–t
VDD[1 – exp (─────)]
vo(t)
R↓(t) C
──── = ───────────────
R↑(t)
R↑(t)
Lectures 3, 4: CMOS Circuits
22
iscmax, Rise Time and Capacitance
i
Small C
vo(t)
Large C
vo(t)
1
────
R↑(t)
iscmax
t
tf
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
23
Psc, Rise Times, Capacitance
For given input rise and fall times short
circuit power decreases as output
capacitance increases.
 Short circuit power increases with increase
of input rise and fall times.
 Short circuit power is reduced if output rise
and fall times are longer than the input rise
and fall times.

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
24
Summary: Short-Circuit Power




Short-circuit power is consumed by each
transition (increases with input transition time).
Reduction requires that gate output transition
should not be faster than the input transition
(faster gates can consume more short-circuit
power).
Increasing the output load capacitance reduces
short-circuit power.
Scaling down of supply voltage with respect to
threshold voltages reduces short-circuit power;
completely eliminated when VDD ≤ |Vtp| + Vtn .
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
25
Components of Power

Dynamic

Signal transitions
 Logic
activity
 Glitches


Static

Copyright Agrawal, 2011
Short-circuit
Leakage
Lectures 3, 4: CMOS Circuits
26
Leakage Power
IG
Ground
Gate
VDD
R
Source
Drain
n+
Bulk Si (p)
Isub
IPT
IGIDL
n+
ID
nMOS Transistor
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
27
Leakage Current Components
Subthreshold conduction, Isub
 Reverse bias pn junction conduction, ID
 Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
 Drain source punchthrough, IPT due to
short channel and high drain-source
voltage
 Gate tunneling, IG through thin oxide; may
become significant with scaling

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
28
Drain to Source Current
IDS = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
29
IDS for Short Channel Device
IDS= μ0 Cox(W/L)Vt2 exp{(VGS –VTH + ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron
Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
30
Subthreshold Current, Isub

Example: 90nm CMOS inverter
L
= 90nm, Wp = 495nm, Wn = 216nm
 Temperature 300K (room temperature)
 Input set to 0 volt
 Vthn = 0.291V, Vthp =0.209V at VDD = 1.2V (nominal)
 PTM (predictive technology model)
 Spice simulation for leakage current
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
31
Subthreshold Current, Isub
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
32
Subthreshold Current, Isub
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
33
Increased Subthreshold Leakage
Log (Drain current)
Scaled device
Ic
Isub
0 VTH’ VTH
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
Gate voltage
34
Summary: Leakage Power




Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply off in unused parts can save power.
For a gate it is a small fraction of the total power;
it can be significant for very large circuits.
Scaling down features requires lowering the
threshold voltage, which increases leakage
power; roughly doubles with each shrinking.
Multiple-threshold devices are used to reduce
leakage power.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
35
CMOS Gate Power
R = Ron
V
i(t)
vi (t)
Large
resistance
v(t)
v(t)
i(t)
C
isc(t)
isc(t)
Ground
Leakage
current
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
time
36
Technology Scaling
Scaling down 0.7 micron by factors 2 and
4 leads to 0.35 and 0.17 micron
technologies
 Constant electric field assumed

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
37
Constant Electric Field Scaling
B. Davari, R. H. Dennard and G. G.
Shahidi, “CMOS Scaling for High
Performance and Low Power—The Next
Ten Years,” Proc. IEEE, April 1995, pp.
595-606.
 Other forms of scaling are referred to as
constant-voltage and quasi-constantvoltage.

Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
38
Bulk nMOSFET
Polysilicon
Gate
Drain
W
Source
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
39
Technology Scaling



A scaling factor (S ) reduces device dimensions as
1/S.
Successive generations of technology have used a
scaling S = √2, doubling the number of transistors
per unit area. This produced 0.25μ, 0.18μ, 0.13μ,
90nm and 65nm technologies, continuing on to
45nm, 32nm and 22nm.
A 5% gate shrink (S = 1.05) is commonly applied to
boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston:
Pearson Addison-Wesley, 2005, Section 4.9.1.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
40
Constant Electric Field Scaling
Device Parameter
Scaling
Length, L
1/S
Width, W
1/S
Gate oxide thickness, tox
1/S
Supply voltage, VDD
1/S
Threshold voltages, Vtn, Vtp
1/S
Substrate doping, NA
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
S
41
Constant Electric Field Scaling(Cont.)
Device Characteristic
β
Scaling
W / (L tox)
S
β (VDD – Vt ) 2
1/S
Resistance, R
VDD / Ids
1
Gate capacitance, C
W L / tox
1/S
Gate delay, τ
RC
1/S
Clock frequency, f
1/ τ
S
CV 2 f
1/S 2
Current, Ids
Dynamic power per gate, P
1/S 2
Chip area, A
Power density
P/A
1
Current density
Ids /A
S
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
42
Problem: A Design Example


A battery-operated 65nm digital CMOS device is found
to consume equal amounts (P ) of dynamic power and
leakage power. The short-circuit power is negligible.
The energy consumed by a computing task, that takes
T seconds, is 2PT.
Compare two power reduction strategies for extending
the battery life:
A.
B.
Clock frequency is reduced to half, keeping all other
parameters constant.
Supply voltage is reduced to half. This slows the gates down
and forces the clock frequency to be lowered to half of its
original (full voltage) value. Assume that leakage current is
reduced by a ratio 10/2 = 5 (see slides 32 and 33).
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
43
Solution: Strategy A. Clock
Frequency Reduction


Reducing the clock frequency will reduce
dynamic power to P / 2, keep the static
power the same as P, and double the
execution time of the task.
Energy consumption for the task will be,
Energy = (P / 2 + P ) 2T = 3PT
which is greater than the original 2PT.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
44
Solution: Part B. Supply Voltage
Reduction


When the supply voltage and clock frequency
are reduced to half their values, dynamic power
is reduced to P / 8 and static power to P / 10.
The time of task is doubled and the total energy
consumption is,
Energy = (P / 8 + P / 10) 2T = 9PT / 20 =0.45PT
The voltage reduction strategy reduces energy
consumption while a simple frequency
reduction consumes more energy.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
45
Comparing Strategies A and B
Original
A
B
Voltage
V
V
V/2
Clock Frequency
F
F/2
F/2
Task Duration
T
2T
2T
Power
2P
1.5P
0.225P
Energy
2PT
3PT
0.45PT
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits
46