Logic simulator and fault diagnosis
Fan Wang
Dept. of Electrical & Computer Engineering
Auburn University
ELEC7250 Term Project Spring 06’
Motivations
Write a compiler for the hierarchical bench
format.
Write a logic simulator for combinational
circuit
Attempt to diagnose the design error
Compiler
Simulation table Example
(generated by matlab)
For hierarchical bench
format, the compiler can
flatten it
Compiler can use
flattened netlist to
generate the simulation
table
For convenience, this
part is implemented by
Matlab.
INPUT: 0
INPUT: 1
INPUT: 2
OUTPUT: 15
OUTPUT: 16
Gatetype: XOR
Gatename: XOR1
Fanin_List: 2 1
Fanout_List: FA_1_1
/***************************/
Gatetype: AND
Gatename: AND1
Fanin_List: 1 2
Fanout_List: FA_1_2
/***************************/
Gatetype: AND
Gatename: AND2
Fanin_List: 0 FA_1_1
Fanout_List: FA_1_3
/***************************/
Gatetype: XOR
Gatename: XOR2
Fanin_List: FA_1_1 0
Fanout_List: 3
/***************************/
Logic Simulation
1. Read vector to the PI
2. Initialize all the PO, Internal nodes as
unknown states (-1).
3. Propagate the value from PI to PO.
For each unknown internal node, search all file until it gets
value. If all the PO get value, step 3 end.
4. Repeat 1 to get the next vector.
* Implemented by C program
Logic Simulation (Cont.)
Num. of vectors vs. Exe. Time
(4-bit ripple carry adder using exhaustive set of vectors)
0.45
CPU time (seconds)
0.4
0.35
0.3
0.25
Series1
0.2
0.15
0.1
0.05
0
1
10 20 30 40 50 100 150 200 250 300 350 400 450 512
Number of vectors
Num. of gates vs. Exe. Time
(1000 random vectors fro ISCAS85 circuits)
@Ultra-5 sparc SUN station
50
45
Exe. Time (minutes)
40
35
30
25
Series1
20
15
10
5
0
6
120
162
320
506
603
number of gates
1179
1726
3284
Some Comments on logic simulator
 The search based algorithm:
1. Time complexity is O( N 2), N: the number of
gates. The worst case is, all gates are list in
reverse order. The time complexity is
The depth of circuit x N 2
2. The levelization of the circuit, the time
complexity will the same as the logic simulation
based search based algorithm
 Better algorithm can be used: link list based
algorithm
Diagnosis
(Sensitized Path Segmentation + PO trace back)
Check PO, see whether the PO get values as expected
If error happens:
1. trace back from the error PO to PI to check the paths
(PATH 1).
2. check which path is sensitized by the vector from PI to
PO (PATH 2).
The error is on the path : PATH 1
* Not for multiple fault diagnosis
 PATH2
Sensitized path segmentation
1
and1
2
p3
Design error: OR --> AND !!
5
p2
or1
8
10
3
9
p1
xor1
and2
4
(PI) 1 2 3 4
(PO Good Value)
(PO Bad Value)
V1
0001
0
0
V2
0011
0
1
V3
1111
0
0
V4
1011
0
1
* Based on 4 vectors: error is on p3  p2  p1
Thanks!