ELEC 5200-001/6200-001
Computer Architecture and Design
Spring 2016
Microprogramming (Appendix D)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
vagrawal@eng.auburn.edu
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
1
Alternatives for Control Unit (CU)
Hard-wired (hardware)
– Random logic, programmable logic array (PLA), or ROM
– Fast
– Inflexible
Firmware
– Microprogrammed or microcoded CU
– Control implemented like a computer (microcomputer)
Microinstructions
Microprogram
– Flexible
Software-like changes to instruction set possible
Completely different instruction sets can be emulated
– Speed limited by microcomputer memory
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
2
IRWrite
MemRead
MemWrite
Spring 2016, Mar 21 . . .
RegWrite
0-15
Sign
extend
0-5
ELEC 5200-001/6200-001 Lecture 8
ALUOut Reg.
ALU
ALUSrcB
ALUSrcA
B Reg.
Register file
11-15
RegDst
A Reg.
28-31
16-20
MemtoReg
PCSource
Shift
left 2
21-25
Mem. Data (MDR)
Data
0-25
Instr. reg. (IR)
IorD
Memory
26-31 to
Control
FSM
Addr.
PC
PCWrite
etc.
Multicycle Datapath
4
Shift
left 2
ALU
control
ALUOp
3
Multicycle Control FSM
Inputs: 6 opcode bits
Outputs: 16 control signals
Start
State 0
1
Instr.
decode/reg.
fetch/branch
addr.
Instr.
fetch/
adv. PC
R
3
2
Read
memory
data
Compute
memory
addr.
lw
5
Write
register
Spring 2016, Mar 21 . . .
B
ALU
operation
6
Write PC
on branch
condition
8
sw
4
J
Write
jump addr.
to PC
9
7
Write
memory
data
Write
register
ELEC 5200-001/6200-001 Lecture 8
4
States and Outputs
Suppose 10 states are encoded 0000 through 1001.
State code completely determines 16 control signals
(Moore machine).
States 0 (0000), 3 (0011) and 6 (0110)
Next state ← present state + 1
State 1 (0001) – opcode determines next state
State 2 (0010) for lw or sw
State 6 (0110) for R-type of instruction
State 8 (1000) for branch instruction
State 9 (1001) for jump instruction
State 2 (0010) – opcode determines next state
State 3 (0011) for lw
State 5 (0101) for sw
States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9
(1001) – next state is unconditionally 0 (0000)
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
5
A Program-Like Implementation
Inputs: 6 opcode bits
Outputs: 16 control signals
Start
State 0000
0001
Instr.
decode/reg.
fetch/branch
addr.
Instr.
fetch/
adv. PC
0011
Read
memory
data
R
0010
lw
Compute
memory
addr.
ALU
operation
J
B
Write PC
on branch
condition
Write
jump addr.
to PC
0110
0100
Write
register
Spring 2016, Mar 21 . . .
0101
sw
1000
1001
0111
Write
memory
data
Write
register
ELEC 5200-001/6200-001 Lecture 8
6
Implementing with ROM
Control
PLA or ROM
16 words
16
16 control
signals
2
4
PLA input or
ROM address
Select
one of
4 ways
Four flip-flops
State sequencer
6-bit
opcode
Spring 2016, Mar 21 . . .
6
ELEC 5200-001/6200-001 Lecture 8
7
ROM and State Sequencer
Control ROM
Sixteen
18-bit words
4-bit address
0001
4-bit state flip-flops
Adder
Advance state
MUX
11 10 01 00
6-bit
Opcode
from IR
Spring 2016, Mar 21 . . .
sw or lw
go to
st. 0
st. + 1
st. 2,6,8,9
st. 3,5
0000
4
Dispatch ROM 2
Control
signals to
datapath
2
AddrCtl
00
11
01
10
Address
4
4
16
Dispatch ROM 1
ROM Address
6
ELEC 5200-001/6200-001 Lecture 8
sw, lw, R,
B or J
8
Dispatch ROM Contents
Each dispatch ROM has sixty-four 4-bit words
Address is 6-bit opcode
Content is next state (4-bits)
Dispatch ROM 1
Dispatch ROM 2
Instruction
Address
(Opcode)
Content
Instruction
Address
(Opcode)
Content
lw
100011
0010
lw
100011
0011
sw
101011
0010
sw
101011
0101
R
000000
0110
B
000100
1000
J
000010
1001
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
9
Control ROM Contents
Control ROM has sixteen
18-bit words:
– bits 0-1, AddrCtl to
control mux
– bits 2-17, sixteen
control signals for
datapath
Address is 4-bit state of
control machine
Spring 2016, Mar 21 . . .
Addr.
bits 17-2
bits 1-0
0000
1001010000001000
11
0001
0000000000011000
01
0010
0000000000010100
10
0011
0011000000000000
11
0100
0000001000000010
00
0101
0010100000000000
00
0110
0000000001000100
11
0111
0000000000000011
00
1000
0100000010100100
00
1001
1000000100000000
00
ELEC 5200-001/6200-001 Lecture 8
10
Microprogram: Basic Idea
The control unit in a computer generates an output
(sequence of control signals) for each instruction.
Suppose we break down each instruction into a series of
smaller operations (microinstructions), such as, fetch,
decode, etc.
Then, implement the control unit as a small computer
(within the computer) that executes a sequence of
microinstructions (microprogram) for each instruction.
M. V. Wilkes, “The Best Way to Design an Automatic
Calculating Machine,” Report of Manchester University
Computer Inaugural Conference, pp. 16-18, 1951.
Reprinted in E. E. Swartzlander (editor), Computer Design
Development: Principal Papers, pp. 266-270, Rochelle
Park, NJ: Hayden, 1976.
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
11
Maurice V. Wilkes
Born June 26, 1913, Staffordshire, UK, died November 29, 2010
1967 Turing Award citation:
Professor Wilkes Is best known
as the builder and designer of the
EDSAC, the first computer with
an internally stored program.
Built in 1949, the EDSAC used a
mercury delay line memory. He is
also known as the author, with
Wheeler and Gill, of a volume on
“Preparation of Programs for
Electronic Digital Computers” in
1951, in which program libraries
were effectively introduced.
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
12
Microcoded Control Unit
Microcode word
Sixteen
Microcode
18-bit words
memory
4-bit address
0001
Address
4
4
μPC 4-bit state flip-flops
16
Control
signals to
datapath
AddrCtl
Sequencing
2
field
MUX
11 10 01 00
Adder
0000
Opcode
from IR
Dispatch ROM 2
lw or sw
Dispatch ROM 1
ROM address
6
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
sw, lw, R,
B or J
Address
select
logic
13
Implementing the Idea
Use a memory type implementation for control
unit.
Create a software infrastructure to automatically
translate instructions into memory data
(microcode):
Microinstructions – define a machine language in which
instructions can be described
Microprogram – an instruction described as a sequence of
microinstructions
Microassembler – converts microprogram to (binary)
microcode
Is there a micro-compiler?
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
14
Microprogramming
A microinstruction set is defined.
To program the control of a computer for an
instruction set, a programmer writes a
microprogram for each machine instruction.
Each micrprogram is converted into
microcode, specific to the datapath
hardware, by a microassembler and the
entire microcode is loaded in the microcode
memory of the control unit (CU).
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
15
Breaking Up MIPS Instructions
R-type instruction:
Fetch
Decode
ALU operation
Write register
lw:
Fetch
Decode
Memory address computation
Read memory
Write register
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
16
Microinstructions for MIPS ISA
Fetch
Decode
RegWr
LWSW1
LW2
SW2
R1
BEQ1
JUMP1
Spring 2016, Mar 21 . . .
fetch instruction
decode instruction, read registers,
calculate branch address
write register
compute memory address
memory read
memory write
register type execution
branch execution
jump execution
ELEC 5200-001/6200-001 Lecture 8
17
Let’s Construct MIPS Instructions
sw:
R-type instruction:
Fetch
Decode
R1
RegWr
Fetch
Decode
LWSW1
SW2
Branch:
lw:
Fetch
Decode
LWSW1
LW2
RegWr
Spring 2016, Mar 21 . . .
Fetch
Decode
BEQ1
Jump:
Fetch
Decode
JUMP1
ELEC 5200-001/6200-001 Lecture 8
18
Microinstruction Format
Just one instruction with seven arguments
A label or name for control state(s), e.g., Fetch, MEM1, etc.
Seven arguments and their possible values:
–
–
–
–
ALU control
SRC1
SRC2
Reg. control
– Memory
– PCWrite
– Sequencing
Spring 2016, Mar 21 . . .
add, subtract or funct. code
# result to ALUOut
PC or A
B, 4, extend or extend-shift
Read
# read two reg. specified by IR into A
and B
Write ALU
# write ALUOut to register file
Write MDR
# register file ← MDR
Read PC
# IR ← M[ PC ]
Read ALU
# MDR ← M[ ALUOut ]
Write ALU
# M[ ALUOut ] ← B
ALU
# write PC from ALU
ALU cond.
# If zero = 1, PC ← ALUOut
Jump addr.
# PC ← jump address
Seq
# choose next μInst. Sequentially
fetch
# go to first μInst. to begin new instr.
Dispatch i
# use Dispatch ROM i, i = 1 or 2
ELEC 5200-001/6200-001 Lecture 8
19
Sequencing Illustrated
State 0
Fetch
Sequencing 1
= seq
Instr.
fetch/
adv. PC
Fetch
Instr.
decode/reg.
fetch/branch
addr.
Dispatch 1
3
2
LW2
Read
memory
data
Compute
memory
addr.
lw
6
5
Write
register
SW2
Write
memory
data
seq
JUMP1
BEQ1
ALU
operation
seq
4
R1
LWSW1
Write PC
on branch
condition
8
Write
jump addr.
to PC
9
7
Write
register
Fetch
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
20
Microinstruction Arguments
Argument
ALU Ctrl
SRC1
SRC2
Value
μCode value
Action
Add
ALUOp = 00
ALU adds
Subt
ALUOp = 01
ALU subtracts for beq
Funct code
ALUOp = 10
ALU executes R-type instruction
PC
ALUSrcA = 0
PC is first ALU input
A
ALUSrcA = 1
Reg A is first ALU input
B
ALUSrcB = 00
Reg B is second ALU input
4
ALUSrcB = 01
Constant 4 is second ALU input
Extend
ALUSrcB = 10
Sign extension unit is second ALU
input
Extshft
ALUSrcB = 11
2-bit shift unit is second ALU input
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
21
Microinstruction Arguments (Cont.)
Argument
Reg. Ctrl
Memory
Value
μCode value
Read
Action
Load A and B from Register file
Write ALU
RegWrite = 1
RegDst = 1
MemtoReg = 0
An IR-specified register in
Register file is written from
ALUOut
Write MDR
RegWrite = 1
RegDst = 0
MemtoReg = 1
An IR-specified register in
Register file is written from MDR
Read PC
MemRead = 1
IorD = 0
IRWrite = 1
IR ← M[ PC ]
MDR ← M[ PC ]
Read ALU
MemRead = 1
IorD = 1
MDR ← M[ ALUOut ]
Write ALU
MemWrite = 1
IorD = 1
M[ ALUOut ] ← B
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
22
Microinstruction Arguments (Cont.)
Field
μInstr. value
μCode value
Action
PCSource = 00
PCWrite = 1
Register file loads A and B
PCSource = 01
PCWriteCond = 1
An IR-specified register in
Register file is written from
ALUOut
PCSource = 10
PCWrite = 1
An IR-specified register in
Register file is written from MDR
AddrCtl = 11
Choose next μInstr. sequentially
AddrCtl = 00
Go to first μInstr. to begin new
instruction
Dispatch 1
AddrCtl = 01
Use Dispatch ROM 1
Dispatch 2
AddrCtl = 10
Use Dispatch ROM 2
PC Write ALU
Ctrl
ALUOutcond
Jump
address
Sequenc Seq
ing
Fetch
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
23
Microinstruction Fetch
Label ALU
ctrl.
SRC1 SRC2 Reg.
ctrl.
Mem.
PCWrite
ctrl.
Fetch
Add
Decode Add
PC
PC
Read PC
ALU
Read
Seq
Dispatch 1
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
Addrctl
PCSource
PCWrite
PCWriteCond
MemRead
IorD
IRWrite
MemWrite
RegWrite
RegDst
MemtoReg
ALUSrcB
Microassembler produces the following microcode:
0
01
0 0 0 1 0 1 0
00 1 0
11
0
11
0 0 0 0 0 0 0
00 0 0
01
ALUSrcA
ALUOp
00
00
4
ExtShft
Seq.
24
Microprogram for lw and sw
Label ALU
ctrl.
SRC1 SRC2 Reg.
ctrl.
LWSW1 Add
LW2
RegWr
SW2
A
Mem.
PCWrite
ctrl.
Extend
Read ALU
Write MDR
Write ALU
Seq.
Dispatch 2
Seq
Fetch
Fetch
Microprogram consists of four microinstructions.
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ELEC 5200-001/6200-001 Lecture 8
25
Microprogram for R-Type Instruction
Label ALU
ctrl.
SRC1 SRC2 Reg.
ctrl.
R1
RegWr
A
Funct code
Mem.
PCWrite
ctrl.
B
Write ALU
Seq.
Seq
Fetch
Go to next μInstr.
Go to μInstr. Fetch
Microprogram consists of two microinstructions.
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
26
Microprogram for beq Instruction
Label ALU
ctrl.
SRC1 SRC2 Reg.
ctrl.
BEQ1
A
Subt
Mem.
B
PCWrite
ctrl.
Seq.
ALUOut-cond
Fetch
If (zero) then PC ← ALUOut
Go to μInstr. Fetch
Microprogram consists of one microinstruction.
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ELEC 5200-001/6200-001 Lecture 8
27
Microprogram for jump Instruction
Label ALU
ctrl.
SRC1 SRC2 Reg.
ctrl.
JUMP1
Mem.
PCWrite
ctrl.
Seq.
Jump address
Fetch
Microprogram consists of one microinstruction.
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
28
μProgram for Multi-Cycle CU
Label
ALU
ctrl.
SRC1
SRC2
Fetch
Add
Decode1 Add
PC
PC
4
ExtShft
LWSW1 Add
LW2
RegWr
SW2
A
Extend
R1
RegWr
FntCd.
A
BEQ1
Subt
Reg.
ctrl.
Mem.
PCWrite
ctrl.
Seq.
Read PC
ALU
Seq
Disp. 1
Read
Disp. 2
Seq
Fetch
Fetch
Read ALU
Write MDR
Write ALU
B
Seq
Fetch
Write ALU
A
B
JUMP1
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
ALUOut-cond
Fetch
Jump address
Fetch
29
IRWrite
MemRead
MemWrite
Spring 2016, Mar 21 . . .
RegWrite
0-15
Sign
extend
0-5
ELEC 5200-001/6200-001 Lecture 8
ALUOut Reg.
ALU
ALUSrcB
ALUSrcA
B Reg.
Register file
11-15
RegDst
A Reg.
28-31
16-20
MemtoReg
PCSource
Shift
left 2
21-25
Mem. Data (MDR)
Data
0-25
Instr. reg. (IR)
IorD
Memory
26-31 to
Microcoded
Control
Addr.
PC
PCWrite
etc.
Multicycle Datapath
4
Shift
left 2
ALU
control
ALUOp
30
Microcode Operation
μPC is always initialized to 0000
Load starting instruction address in PC
Clock control and datapath
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
31
How Microcode Works
0001 in clk 2
0001
4
4
Sixteen
Microcode
18-bit words
memory
4-bit address
μPC
Address
0000
16
clk 1: Set
Datapath
for Fetch
AddrCtl
Sequencing
11
field
MUX
11 10 01 00
Adder
0000
Opcode
from IR
In clk 2
Dispatch ROM 2
lw or sw
Dispatch ROM 1
ROM address
6
Spring 2016, Mar 21 . . .
ELEC 5200-001/6200-001 Lecture 8
sw, lw, R,
B or J
Address
select
logic
32
Multicycle Control FSM
Inputs: 6 opcode bits
Outputs: 16 control signals
Start
State 0
1
Instr.
decode/reg.
fetch/branch
addr.
Instr.
fetch/
adv. PC
R
3
2
Read
memory
data
Compute
memory
addr.
lw
5
Write
register
Spring 2016, Mar 21 . . .
B
ALU
operation
6
Write PC
on branch
condition
8
sw
4
J
Write
jump addr.
to PC
9
7
Write
memory
data
Write
register
ELEC 5200-001/6200-001 Lecture 8
33
Summary
Hard-wired control: A finite state machine
implemented typically using programmable logic
array (PLA) or random logic.
Microinstruction: A one-clock instruction that
asserts a set of control signals to the datapath and
specifies what microinstruction to execute next.
Microprogram: A sequence of microinstructions
that implements a multicycle (or single cycle)
instruction.
Microcode: Machine code of a microprogram,
generally produced by a microassembler.
Microprogrammed or microcoded control: A
method of specifying control that uses microcode
rather than a finite state machine.
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ELEC 5200-001/6200-001 Lecture 8
34
Further on Microprogramming
Preceding discussion is based on:
D. A. Patterson and J. L. Hennessey, Computer Organization and
Design, Second Edition, San Francisco: Morgan-Kaufman, 1998,
Chapter 5, pp. 399-410.
Terms “microcomputer”, “microarchitecture” and
“micropipeline” are not related to microprogramming.
Nanoprogramming: Two levels of microprogramming
– a “recursive” control:
Nanodata Corp., QM-1 Hardware Level Users Manual, 2nd Ed.,
Williamsville, NY, 1972.
J. P. Hayes, Computer Architecture and Organization, Section
4.4.3, NY: McGraw-Hill, 1978.
Virtual machines: Any program can be run on any
instruction set using an interpreter. Example, Java.
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ELEC 5200-001/6200-001 Lecture 8
35