Effect of Variation of threshold voltage on
power consumption, delay and area of a
32x32 bit array Multiplier
ELEC 6970: Low Power Design
Class Project
By: Sachin Dhingra
Outline
 Introduction
 Design of the multiplier
 Background
 Leakage Power
 Threshold Voltage
 Results
 Conclusion
 Future Work
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Introduction
 Design and Verification of an array
multiplier using VHDL
 Reduction of leakage current of the circuit
by variation of the threshold voltage (Vt)
 Sub-threshold conduction current decreases as
the Vt increases
 Increase in Vt also leads to higher switching
delays
 Aim: To reduce the leakage current by
varying the threshold voltage of the
transistors and observe its effect on the
overall power consumption, delay and area
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Leakage Power


Leakage Power components





Sub-threshold Leakage current
Reverse bias p-n junction conduction
Gate induced drain leakage
Drain source punch through (Short channel effects)
Gate tunneling


Carrier diffusion between the source and the drain region of the transistor
Grows exponentially as Vt decreases
Sub-threshold Leakage current
VDD
IG
Ground
R
n+
Isub
n+
IPT
IGIDL
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ID
I sub  I ds  I 0e
 Vgs Vt

 nvth



(1  e
 Vds 


 vth 
Where,
Vt – Threshold voltage
I0 – Ids @ cutoff i.e. Vgs = Vt
n – experimentally derived constant
ELEC 6970: Low Power Design
4
)
Threshold Voltage

Threshold Voltage is given by the
expression:
Vt = Vt0 + γ[(Φs+Vsb)½- Φs½]
Where,


Vt0 - Threshold voltage when source
is at body potential
γ – Body effect parameter


Φs – Surface potential



Function of doping level, permittivity
and oxide thickness
function of thermal voltage and
doping level
Vsb – Source to Body voltage
Hence, Threshold Voltage is a
function of:



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Doping concentration
Thickness of oxide
Source to Body Voltage
ELEC 6970: Low Power Design
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Threshold Voltage
 Increase in Threshold Voltage
 Reduction of Leakage power due to decrease in
Sub-threshold conduction
 Increase in gate delay
 α ~ 1 for short channel devices
 Vt variation
 Body bias control
 Vt is a function of Vsb
KVDD
Delay 
VDD  Vt 
 Vt increases as Vsb increases
 Change in process parameters
 Doping concentration
 Oxide thickness
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Multiplier Design and Analysis
B3
 The multiplier was designed in
VHDL using nested conditional
generate statements and port
mapping
 Synthesis and Critical path
analysis was done using
Leonardo
0
B2
B1
0
B0
0
0
A0
0
A1
0
A2
0
A3
 TSMC 0.25µm library
 Timing and Power analysis was
done using ELDO
 TSMC 0.25µm library
 TSMC 0.18µm library
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0
Y6
Y5
Y4
Y3
Array
Critical Path
(using Leonardo)
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Cell
 Area: 7 gates
 1 x 2:1 MUX (2 gates)
 2 x XNOR2 (2 gates)
 1 x AND2
 Critical paths
B
Sum input
A
Carry out
Carry in
Full
adder
Sum output
 A → Cout
 B → Cout
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Multiplier
 4x4
 Area: 82 gates
 Critical paths
 A0 → Y7
 B2 → Y7
 A1 → Y7
B3
0
B2
B1
0
B0
0
0
A0
0
A1
0
 32x32
A2
 Area: 6995 gates
 Critical paths
 A0 → Y63
 B2 → Y63
 A1 → Y63
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ELEC 6970: Low Power Design
0
A3
0
Y7
Y6
Y5
Y3
9
Vt variation: Cell
Vt
(NMOS)
Vt
(PMOS)
∆Vt (V)
Leakage
power (pW)
Average
Power (µW)
Delay
(ps)
0.28
-0.29
-0.2
794795
29.52
65.36
0.38
-0.39
-0.1
4772
28.62
69.8
0.43
-0.44
-0.05
1204.1
27.51
72.12
0.48
-0.49
0
351.62
26.39
74.33
0.58
-0.59
0.1
100.91
25.57
80.07
0.68
-0.69
0.2
86.16
24.34
87.01
0.88
-0.89
0.4
84.3
22.83
106.79
1.08
-1.09
0.6
83.457
21.93
137.02
1.48
-1.49
1
81.74
20.25
253.84
1.68
-1.69
1.2
80.89
19.61
379.88
2.08
-2.09
1.6
79.2
18.54
1335.96
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Power and Delay analysis
1600
1400
1200
Leakage power (pW)
1000
Delay (ps)
800
600
400
200
0
-0.4
-0.2
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0
0.2
0.4
0.6
0.8
Change in Vth (V)
1
ELEC 6970: Low Power Design
1.2
1.4
1.6
1.8
11
Power Delay Product
350000
300000
250000
200000
Power Delay Product
150000
100000
50000 Optimum Value ~ +0.2
0
-0.2
0
0.2
0.4
0.6
0.8
1
Change in Vth (V)
1.2
1.4
1.6
1.8
The optimal threshold voltage for the cell design which gives the best
tradeoff between Leakage Power and Delay is approximately:
+0.7V for NMOS & -0.7V for PMOS
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Conclusion
 The Leakage Power reduced as the
threshold voltage was increased
 The Delay of the cell also increased as we
incremented Vt
 Area of the circuit remained unaffected
 Power – Delay product was evaluated to
find the optimum value of Vt for the given
cell design




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∆Vt ~ 0.2 V
Leakage Power reduction = 75%
Delay increase = 17%
Total Power reduction = 8%
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Future Work
 Variation of threshold using Body bias Voltage
 New Library design required
 Results for Multipliers of different sizes
 Extrapolation of results for larger multipliers
 Dual threshold design
 Threshold assignment algorithm
 Analysis of Delay and Power
 Analysis of Power and Delay for different design libraries
 TSMC 0.18 µm
 TSMC 0.13 µm
 Detailed study of power estimation and timing analysis
tools
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