ELEC 5970-001/6970-001(Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Power Consumption in a CMOS Circuit
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
vagrawal@eng.auburn.edu
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ELEC5970-001/6970-001 Lecture 2
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Class Projects
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Study of leakage dynamic power in nanometer devices
Low leakage technologies
Charge recovery and adiabatic switching circuits
Simulation-based power estimation tool
Transistor-sizing for low power
Logic and flip-flop design for low power
Low power clock distribution
Low power arithmetic circuits
Low power memory design
Benchmarking of low power microprocessors
Low power system design
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Components of Power
• Dynamic
– Signal transitions
• Logic activity
• Glitches
– Short-circuit
• Static
– Leakage
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Ptotal =
Pdyn + Pstat
Ptran + Psc + Pstat
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Power of a Transition: Ptran
VDD
Ron
ic(t)
vi (t)
R=large
vo(t)
CL
Ground
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Charging of a Capacitor
R
t=0
v(t)
i(t)
C
V
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
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=
dq(t)/dt
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C dv(t)/dt =
[V – v(t)] /R
dv(t)
V – v(t)
───
=
─────
dt
RC
dv(t)
dt
∫ ───── =
∫─────
V – v(t)
RC
-t
ln [V – v(t)]
=
── + A
RC
i(t)
=
Initial condition, t = 0, v(t) = 0 → A = ln V
-t
v(t) =
V [1 – exp(───)]
RC
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v(t) =
i(t)
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=
-t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
V
-t
── exp( ── )
R
RC
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Total Energy Per Charging
Transition from Power Supply
Etrans =
=
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∞
∫ V i(t) dt =
0
∞ V2
-t
∫ ── exp( ── ) dt
0 R
RC
CV2
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Energy Dissipated per Transition in
Resistance
∞2
R ∫ i (t) dt
0
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=
V2 ∞
-2t
R ──
∫ exp( ── ) dt
2
R 0
RC
=
1
─ CV2
2
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Energy Stored in Charged
Capacitor
∞
∫ v(t) i(t) dt
0
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∞
-t V
-t
= ∫ V [1-exp( ── )] ─ exp( ── ) dt
0
RC R
RC
1
= ─ CV2
2
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Transition Power
• Gate output rising transition
– Energy dissipated in pMOS transistor = CV2/2
– Energy stored in capacitor = CV2/2
• Gate output falling transition
– Energy dissipated in nMOS transistor = CV2/2
• Energy dissipated per transition = CV2/2
• Power dissipation:
Ptrans =
Etrans α fck =
α fck CV2/2
α
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=
activity factor
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Short Circuit Current, isc(t)
VDD
VDD - VTp
Vi(t)
Volt
Vo(t)
VTn
0
Iscmaxf
isc(t)
Amp
0
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tB
tE
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Time (ns)
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Peak Short Circuit Current
• Increases with the size (or gain, β) of
transistors
• Decreases with load capacitance, CL
• Largest when CL= 0
• Reference: M. A. Ortega and J. Figueras,
“Short Circuit Power Modeling in
Submicron CMOS,” PATMOS’96, Aug.
1996, pp. 147-166.
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Short-Circuit Energy per Transition
• Escf =∫
tE
tB
VDD isc(t)dt = (tE – tB) IscmaxfVDD /2
• Escf = tf (VDD- |VTp| -VTn) Iscmaxf /2
• Escr = tr (VDD- |VTp| -VTn) Iscmaxr /2
• Escf = 0, when VDD = |VTp| + VTn
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Short-Circuit Energy
• Increases with rise and fall times of input
• Decreases for larger output load
capacitance
• Decreases and eventually becomes zero
when VDD is scaled down but the
threshold voltages are not scaled down
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Short-Circuit Power Calculation
• Assume equal rise and fall times
• Model input-output capacitive coupling
(Miller capacitance)
• Use a spice model for transistors
– T. Sakurai and A. Newton, “Alpha-power Law
MOSFET model and Its Application to a
CMOS Inverter,” IEEE J. Solid State Circuits,
vol. 25, April 1990, pp. 584-594.
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Short Circuit Power
Psc =
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α fck Esc
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Psc vs. C
0.7μ CMOS
45%
Psc/Ptotal
3ns
0%
35
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Decreasing Input
rise time
0.5ns
C (fF)
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Psc, Rise Time and Capacitance
VDD
Ron
ic(t)+isc(t)
vo(t)
vi (t)
tf
CL
R=large
Ground
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tr
vo(t)
───
R↑
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isc, Rise Time and Capacitance
Isc(t) =
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-t
VDD[1- exp(─────)]
vo(t)
R↓tf (t)C
──── = ──────────────
R↑tf (t)
R↑tf (t)
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iscmax, Rise Time and Capacitance
i
Small C
vo(t)
Large C
vo(t)
1
────
R↑tf (t)
iscmax
t
tf
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Psc, Rise Times, Capacitance
• For given input rise and fall times short
circuit power decreases as output
capacitance increases.
• Short circuit power increases with increase
of input rise and fall times.
• Short circuit power is reduced if output rise
and fall times are smaller than the input
rise and fall times.
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Technology Scaling
• Scale down by factors of 2 and 4, i.e.,
model 0.7, 0.35 and 0.17 micron
technologies
• Constant electric field assumed
• Capacitance scaled down by the
technology scale down factor
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Bulk nMOSFET
Polysilicon
Gate
Drain
W
Source
n+
n+
L
p-type body (bulk)
SiO2
Thickness = tox
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Scaling Factor, α
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Constant electric field
L=L/α
W=W/α
tox = tox / α
VDD = VDD/α
Capacitance → 1/α
Gate delay → 1/α
Area → 1/α2
Power dissipation → 1/α2
Power density constant
Doping → α
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Technology Scaling Results
L=0.17μ, C=10fF
Psc/Ptotal
70%
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60%
L=0.35μ, C=20fF
37%
16%
12%
4%
1%
0.4
L=0.7μ, C=40fF
Input tr or tf (ns)
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Effects of Scaling Down
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1-16% short-circuit power at 0.7 micron
4-37% at 0.35 micron
12-60% at 0.17 micron
Reference: S. R. Vemuru and N.
Steinberg, “Short Circuit Power Dissipation
Estimation for CMOS Logic Gates,” IEEE
Trans. on Circuits and Systems I, vol. 41,
Nov. 1994, pp. 762-765.
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Summary: Short-Circuit Power
• Short-circuit power is consumed by each
transition (increases with input transition time).
• Reduction requires that gate output transition
should not be faster than the input transition
(faster gates can consume more short-circuit
power).
• Increasing the output load capacitance reduces
short-circuit power.
• Scaling down of supply voltage with respect to
threshold voltages reduces short-circuit power.
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Components of Power
• Dynamic
– Signal transitions
• Logic activity
• Glitches
– Short-circuit
• Static
– Leakage
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Leakage Power
IG
Ground
VDD
R
n+
Isub
IPT
IGIDL
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n+
ID
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Leakage Current Components
• Subthreshold conduction, Isub
• Reverse bias pn junction conduction, ID
• Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
• Drain source punchthrough, IPT due to
short channel and high drain-source
voltage
• Gate tunneling, IG through thin oxide
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Subthreshold Current
Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt}
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
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IDS for Short Channel Device
Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH+ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
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Increased Subthreshold Leakage
Scaled device
Log Isub
Ic
0 VTH’ VTH
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Gate voltage
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Summary: Leakage Power
• Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply off in unused parts can save power.
• For a gate it is a small fraction of the total power;
it can be significant for very large circuits.
• Scaling down features requires lowering the
threshold voltage, which increases leakage
power; roughly doubles with each shrinking.
• Multiple-threshold devices are used to reduce
leakage power.
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