Reconvergent Fanout Analysis
of Bounded Gate Delay Faults
Master’s Defense
Hillary Grimes
Thesis Advisor: Dr. Vishwani D. Agrawal
Thesis Committee: Dr. Victor P. Nelson and Dr. Charles E. Stroud
Dept. of ECE, Auburn University
Auburn, AL 36849
1
Outline
• Background
• Problem Statement
• Ambiguity Lists
Fault-Free Circuit Simulation
Detection Threshold Evaluation
• Experimental Setup
• Results and Discussion
• Conclusions
2
Delay Testing
• Delay testing ensures a manufactured
design meets it’s timing specifications
• Gate Delay Fault Model
Assume that a delay fault is lumped at a faulty
gate
All other gates have their delays within the
specified (min, max) range.
3
A Gate Delay Test
• A delay test consists of a vector pair
First vector (V1) initializes the circuit
Second vector (V2) produces the required
transitions
• For a slow-to-rise gate delay fault:
V1 – places a logic 0 at the fault site
V2 – stuck-at-0 test for the same fault site
4
Fault-Free Circuit Simulation
• IV – initial value for V1-V2 transition – stable
logic value at gate after V1 is applied
• FV – final value for V1-V2 transition – stable
logic value at gate after V2 is applied
• EA – earliest arrival time for gate output
after V2 is applied
• LS – latest stabilization time for gate output
after V2 is applied
5
Fault-Free Circuit Simulation
0
1
3
3
1,3
5
1,2
4
EA = 0
LS = 0
1,2
1,2
2
1
11
5
IV = 1
1
1,3
EA = ∞
LS = -∞
FV = 0
3,4
5
EA = 5
9
LS = 9
6
Faulty Waveforms
• Faulty Propagating Value - FPV
Signal’s logic value in the presence of a stuckat-IV fault at the fault site
• Propagates the fault’s logic effect through
the circuit
• Used to determine whether or not a delay
fault of any size (transition fault) is
detected
7
Fault Propagating Values
0
1,3
1
3
3
5
1,2
4
Slow-To
Fall
1
1,2
11
1,2
2
5
1
1,3
3,4
5
9
8
Fault Propagating Values
0
1,3
1
FPV = 1
3
3
5
1,2
FPV = 1
4
FPV = 0
FPV = 0
1,2
1,2
2
1
1
1,3
FPV = 1
11
5
3,4
FPV = 1
5
FPV ≠ FV
Assuming the delay
fault size is large
9
enough, it is detected
9
Detection Threshold
• For gate delay faults, we also need to
know the size (δ) of faults detected
• Detection Threshold – minimum size delay
fault detectable by the test
• Requires timing information about faulty
waveforms to be propagated along with
FPVs
RTa & RTb – signal is at FPV between the times
RTa to RTb+δ
10
Detection Threshold Evaluation
0
1
1,3
3
1
1,2
FPV = 1
RTa = -∞
RTb = 1
1,2
1,3
3
5
4
2
5
FPV = 0
RTa = -∞
RTb = 2
1
FPV = 1
Ts = 12
RTa = -∞
RTb = 3
FPV = 1
3,4
1,2
RTa = -∞
RTb = 5
FPV = 1
RTa = -∞
RTb = ∞
5
9
11
FPV = 0
RTa = -∞
RTb = 4
Ts and RTb at the
output determine
detection threshold
11
Detection Threshold Evaluation
FPV = 0
RTa = -∞
RTb = 4
Ts = 12
4
11
Detection Threshold = 8
• The output signal is at FPV between times
RTa  (RTb+δ): -∞  (4+δ)
• Detection Threshold is Ts – RTb: (12-4)=8
Fault detected if it’s size is greater than 8:
δ>8
12
Detection Gap
• Calculating the “detection gap” provides a
way to relate the detection threshold of a
detected gate delay fault to the slack at
the fault site
• Detection gap is: DT(G) – slack(G)
DT(G)  detection threshold at fault site G
slack(G)  sum of all minimum gate delays
along the longest delay path through G
13
Detection Gap
• The smaller the detection gaps are for a
set of vectors, the better quality that set
provides for detecting gate delay faults
• If a test detects a fault with gap = 0:
The smallest possible gate delay fault has been
detected
• If detection gap > 0:
There is a possibility a better test exists to
detect the fault with a smaller threshold
14
An Illustration of Detection Gap
PI
p1 - longest delay
path through gate
Ts
PO
p1
delay
Gate
p2
slack
gap
p2
delay
DT(p2)
• A test that detects the fault through path
p1 would be better than a test that detects
the fault through path p2
15
Problem Statement
• When signals produced by a common
fanout point reconverge, the inputs to the
reconvergent gate are correlated
• Conventional simulation ignores this
correlation when bounded gate delays are
used
Produces pessimistic results in both bounded
delay simulation and gate delay fault simulation
16
Reconvergent Fanout Analysis
Fall occurs at time ‘x’
0
Hazard cannot occur
1x 3
3
1,3
5
1,2
4
1,2
6
11
1,2
x+1 5
1
1
3,4
1,3
Output rises at least 1
unit after ‘x’
5
9
17
Correct Detection Threshold
Ts = 12
FPV = 0
RTa = - ∞
RTb = 6
4
6
11
Detection Threshold = 6
• The output signal is at FPV between times
RTa to RTb+δ
• In an accurate analysis, RTb=6, not 4
Fault detected if it’s size is greater than 6:
δ>6
18
Ambiguity Lists
• Ambiguity Lists generated at fanout points
contain
originating fanout name
ambiguity interval – min and max delays from
fanout to gate
• Ambiguity lists at the inputs of a
reconvergent gate help determine its output
19
Ambiguity Lists
• List propagation is similar to fault list
propagation in concurrent fault simulation
• For accurate detection threshold evaluation,
ambiguity lists are propagated during both
fault-free and faulty waveform calculations
20
Ambiguity Lists – Fault-Free
Circuit
• Ambiguity lists propagated through all
gates during fault-free circuit simulation
• If signal correlations are such that no
hazard can occur, the hazard is
suppressed: (EA = ∞) & (LS = -∞)
• Otherwise, the ambiguity lists are
propagated to the gate’s output, and
ambiguity intervals are updated
21
Fault-Free Circuit Simulation
EA = ∞
LS = -∞
0
1,3
EA = 0
LS = 0
1
3
1,2
EA = 1
LS = 3
3
5
4
1,2
2
5
1,2
EA = 2
LS = 5
1
1
1,3
EA = ∞
LS = -∞
11
EA = 6
LS = 11
EA = 5
LS = 9
3,4
EA = ∞
LS = -∞
6
5
9
22
Ambiguity Lists – Detection
Threshold Evaluation
• Ambiguity lists propagated through
downcone of the fault site
• If signal correlations are such that no
hazard can occur, the hazard is
suppressed: (RTa = -∞) & (RTb = ∞)
• Otherwise, the hazard lists are propagated
to the gate’s output, and ambiguity
intervals are updated
23
Detection Threshold Evaluation
0
1,3
1
Tc = 12
FPV = 1
RTa = -∞
RTb = ∞
3
FPV = 1
RTa = -∞
RTb = 1
1,2
3
5
4
1,2
1
1
1,3
2
5
FPV = 0
RTa = - ∞
RTb = 2
3,4
FPV = 1
RTa = -∞
RTb = ∞
1,2
FPV = 1
RTa = - ∞
RTb = 5
5
9
6
11
FPV = 0
RTa = - ∞
RTb = 6
Now, RTb at the
output is correctly
evaluated as 6
24
Experimental Setup
• C program implemented to perform gate
delay fault simulation on combinational
circuits
• Simple wireload model used for gate
delays
Bounded delays set to (3.5n ± 14%), where n is
the number of fanouts
Program can accept any available gate delay
data, which may be normally available from
process technology characterization
25
Experimental Setup
• Program inputs
Netlist in bench format
Vector file
• Program outputs for vector set
Average detection gap of detected gate delay
faults
Fault coverage of faults detected with gap ≤ 3.5
26
Experiment A
• Gate delay fault simulation  1,000
vectors
• Ambiguity lists propagated during faulty
waveform calculations only
• Average detection gap and fault coverage
of faults detected with gap ≤ 3.5 (nominal
gate delay) recorded
27
Experiment A
• For fault coverage, faults are counted as
detected if they are detected:
though the longest path through the gate
through a path which is less than the longest
path by only one gate delay
28
Results: Experiment A
Without Reconvergent
Fanout Analysis
Circuit
c432
c499
c880
c1355
c1908
c2670
c3540
c5315
c7552
Average
Detection
Gap
99.7
36.5
19.3
51.3
57.0
40.5
54.1
24.8
41.0
Faults
Detected with
Gap ≤ 3.5
8.83%
5.69%
43.69%
3.80%
15.85%
28.78%
20.07%
42.59%
11.46%
With Reconvergent
Fanout Analysis
Average
Detection
Gap
98.0
35.4
17.0
47.8
51.9
29.9
49.1
8.2
24.8
Faults
Detected with
Gap ≤ 3.5
8.83%
5.69%
43.92%
6.31%
17.66%
31.70%
17.49%
46.79%
20.26%
29
Experiment B
• Bounded delay simulation of the fault-free
circuit  10,000 vectors
• Ambiguity lists propagated through every
gate
• Largest EA and LS values at circuit
outputs for all vectors recorded to
illustrate difference seen at outputs when
ambiguity lists are used
30
Results: Experiment B
Without Reconvergent
Fanout Analysis
Circuit
c3540
C5315
C6288
C7552
Largest EA
96.0
76.8
158.4
91.2
Largest LS
204.0
204.0
576.0
204.0
With Reconvergent
Fanout Analysis
Largest EA
121.6
91.2
236.8
104.0
Largest LS
196.8
194.4
504.0
201.6
• Using reconvergent fanout analysis generally
results in larger EA and smaller LS values at
outputs
• More apparent for circuits that contain a large
number of reconvergent fanouts, such as in
multiplier circuit c6288
31
Experiment C
• Gate delay fault simulation  10,000
vectors
• Ambiguity lists propagated during both
fault-free circuit simulation and detection
threshold evaluation
• Average detection gap and fault coverage
of faults detected with gap ≤ 3.5 recorded
32
Results: Experiment C
Without Reconvergent
Fanout Analysis
Circuit
c432
c499
c880
c1355
c1908
c2670
c3540
c5315
c7552
Average
Detection
Gap
110.4
51.7
16.4
50.8
55.2
41.8
50.4
21.7
39.4
Faults
Detected with
Gap ≤ 3.5
7.35%
4.91%
48.41%
4.80%
21.70%
31.25%
32.60%
55.72%
13.43%
With Reconvergent
Fanout Analysis
Average
Detection
Gap
108.9
44.0
12.9
42.2
47.1
36.0
44.0
6.1
22.5
Faults
Detected with
Gap ≤ 3.5
7.08%
12.85%
48.86%
13.62%
25.10%
36.54%
33.19%
57.31%
22.83%
33
Discussion
• When reconvergent fanout analysis is
used, the average detection gap is smaller
and more faults are detected with smaller
gaps
• To accurately evaluate detection
thresholds, signal correlations must be
considered in both fault-free waveform
and faulty waveform calculations
34
Conclusion
• Propagating ambiguity lists during simulation
provides useful information about signal
correlations due to reconvergent fanouts
• The use of this information during both faultfree and faulty waveform calculations
produces more accurate results for gate delay
fault simulation
• This min-max delay simulator has found
application in hazard-free delay test generation
35
Future Work
• During simulation, ambiguity lists can grow
quite large
Efficiency in list propagation needs to be improved
• Can information provided by propagating
ambiguity lists help reduce pessimism in
static timing analysis?
36
Publications related to this work
• S. Bose, H. Grimes and V. D. Agrawal, “Delay Fault
Simulation with Bounded Gate Delay Model”, in Proc.
IEEE International Test Conference, paper 26.3, 2007.
• H. Grimes and V. D. Agrawal, “Analyzing Reconvergent
Fanouts in Gate Delay Fault Simulation”, in Proc. 17th
IEEE North Atlantic Test Workshop, May 2008.
37
Thank You
38