ELEC 7770
Advanced VLSI Design
Spring 2016
Power and Ground
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16
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ELEC 7770: Advanced VLSI Design (Agrawal)
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References
 Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken,




New Jersey: Wiley, 2004.
M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution
Networks with On-Chip Decoupling Capacitors, Springer, 2008.
C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and
Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and
K.-T. Cheng (Editors), Electronic Design Automation, MorganKaufmann, 2009. pp. 751-850.
J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip
Power/Ground Network Optimization Considering Decap Leakage
Currents,” Proc. Asia and South Pacific Design Automation Conf.,
2005 , pp. 735-738.
Decoupling Capacitors,
http://www.vlsichipdesign.com/index.php/Chip-DesignArticles/decoupling-capacitors.html
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2
Supply Voltage
Supply voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.25
0.18
0.13
0.1
Minimum feature size (μm)
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Gate oxide thickness (A)
Gate Oxide Thickness
60
50
40
30
20
High gate leakage
10
0
0.25
0.18
0.13
0.1
Minimum feature size (μm)
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4
Power Supply Noise
 Transient behavior of supply voltage and ground

level.
Caused by transient currents:
 Power droop
 Ground bounce
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5
Power Supply
V(t)
VDD
–
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R
R
C
C
ELEC 7770: Advanced VLSI Design (Agrawal)
Gate 2
+
Gate 1
Rg
6
Switching Transients
 Only Gate 1 switches (turns on):
V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg)
VDD
V(t)
VDD[1 – Rg/(R+Rg)]
0
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ELEC 7770: Advanced VLSI Design (Agrawal)
time, t
7
Gate output voltage
Multiple Gates Switching
VDD
1
2
3
Number of gates switching
many
0
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ELEC 7770: Advanced VLSI Design (Agrawal)
time, t
8
Decoupling Capacitor
 A capacitor to isolate two electrical circuits.
 Illustration: An approximate model:
i(t)
VL(t)
t=0
Rg
VDD = 1
a
t=0
+
Rd
–
Cd
t
IL
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Approximate Load Current, IL
IL
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0,
t<0
at,
t < tp
a(2tp – t),
t < 2tp
0,
t > 2tp
=
ELEC 7770: Advanced VLSI Design (Agrawal)
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Transient Load Voltage
VL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T) ], 0 < t < tp
T
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=
Cd (Rg + Rd)
ELEC 7770: Advanced VLSI Design (Agrawal)
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Realizing Decoupling Capacitor
VDD
VDD
S
B
D
OR
S
GND
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B
D
GND
ELEC 7770: Advanced VLSI Design (Agrawal)
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Capacitance
Cd =
γ×WL×ε×ε0/Tox
≈
0.26fF, for 70nm BSIM
L
=
38nm,
γ
=
1.5462
ε
=
4
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W
=
ELEC 7770: Advanced VLSI Design (Agrawal)
200nm
13
Leakage Resistance
Igate
=
α × e – βTox ×W
where α and β are technology parameters.
Rd
=
VL(t)/Igate
Because V(t) is a function of time, Rd is
difficult to estimate. The decoupling
capacitance is simulated in spice.
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Power-Ground Layout
Solder bump pads
Vss
Vss
Vdd
M5
Vdd/Vss supply
Vdd/Vss
equalization
M4
Via
Vss
Vdd
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Vdd
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Power Grid
+
–
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Nodal Analysis
V2
g2
g1
g3
Vi
V1
V3
g4
Ci
Apply KCL to node i:
Bi
V4
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4
∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi
k=1
ELEC 7770: Advanced VLSI Design (Agrawal)
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Nodal Analysis
G V – C V’ = B
Where G is conductance matrix
V is nodal voltage vector
C is capacitance matrix
B is vector of currents
V(t) is a function of time, V(0) = VDD
B(t) is a function of time, B(0) ≈ 0 or leakage current
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Wire Width Considerations
 Increase wire width to reduce resistance:
 Control voltage drop for given current
 Reduce resistive loss
 Reduce wire width to reduce wiring area.
 Minimum width restricted to avoid metal
migration (reliability consideration).
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A Minimization Problem
Minimize total metal area:
Where n
wi
si
ρ
Ci
xi
n
∑ wi si
i=1
=
n
∑ | ρ Ci si2 | / xi
i=1
A
=
=
=
=
=
=
=
number of branches in power network
metal width of ith branch
length of ith branch
metal resistivity
maximum current in ith branch
voltage drop in ith branch
Subject to several conditions.
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Condition 1: Voltage Drop
Voltage drop on path Pk:
∑ xi
i ε Pk
Where Δvk
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=
≤
Δvk
maximum allowable voltage drop on
kth path
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Condition 2: Minimum Width
Minimum width allowed by fabrication process:
wi
=
ρ Ci si / xi
Where wi
si
ρ
Ci
xi
W
=
=
=
=
=
=
metal width of ith branch
length of ith branch
metal resistivity
maximum current in ith branch
voltage drop in ith branch
minimum line width
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≥
ELEC 7770: Advanced VLSI Design (Agrawal)
W
22
Condition 3: Metal Migration
Do not exceed maximum current to wire-width ratio:
Ci / wi
Where wi
si
ρ
Ci
xi
σi
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≤
σi
=
xi /(ρ si)
=
=
=
=
=
=
metal width of ith branch
length of ith branch
metal resistivity
maximum current in ith branch
voltage drop in ith branch
maximum allowable current density
across ith branch
ELEC 7770: Advanced VLSI Design (Agrawal)
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Decoupling Capacitance
Rg
VDD
+
Cd
I(t)
–
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Decoupling Capacitance




Initial charge on Cd, Q0 = Cd VDD
I(t): current waveform at a node
T: duration of current
Total charge supplied to load:
T
Q = ∫ I(t) dt
0
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Decoupling Capacitance




Assume that charge is completely supplied by Cd.
Remaining charge on Cd = Cd VDD – Q
Voltage of supply node = VDD – Q/Cd
For a maximum supply noise ΔVDDmax,
VDD – (VDD – Q/Cd) ≤ ΔVDDmax
Or Cd ≥
Q / ΔVDDmax
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ELEC 7770: Advanced VLSI Design (Agrawal)
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A High-Voltage On-Chip Power
Distribution Network
Master’s Thesis
www.eng.auburn.edu/~vagrawal/THESIS/SHIHAB/Mustafa_Thesis.pdf
Mustafa M. Shihab
Auburn University
ECE Department
June 2013
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June 28, 2013
27
On-Chip Power Distribution Network
 Power Distribution ‘Grid’:
Source: N. Weste et al., CMOS VLSI design: A Circuits and Systems
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I2R Power Loss
Take Away: For a 100 mile long line carrying 1000 MW of energy
@ 138 kV power loss = 26.25%
@ 345 kV power loss = 4.2%
@Source:
765 kV power loss = 1.1% to 0.5%
“American Electric Power Transmission Facts “, http://bit.ly/11nUMvf
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ELEC 7770: Advanced29VLSI Design (Agrawal)
I2R Power Loss on a Chip
 I2R Loss in On-Chip Power Distribution Network:
Increasing
Current
Density
Increasing
I2R Loss
Technology
Scaling
Increasing
Wire
Resistivity
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ELEC 7770: Advanced30VLSI Design (Agrawal)
Problem Statement
Propose a scheme for delivering power to different
parts of a large integrated circuit, such as cores on a
system-on-chip (SoC), at a higher than the regular
(VDD) voltage.
The increase in voltage will lower the current on the
grid, and thereby reduces the I2R loss in the on-chip
power distribution network.
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ELEC 7770: Advanced31VLSI Design (Agrawal)
Typical Power Distribution Network
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Proposed Power Distribution Network
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Present Distribution Scheme
 Example: Low-Voltage (VDD) Power Grid with 9 loads
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ELEC 7770: Advanced34VLSI Design (Agrawal)
Proposed Distribution Scheme
 Example: High-Voltage (3V) Power Grid with 9 loads
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ELEC 7770: Advanced35VLSI Design (Agrawal)
Result: Low Voltage Distribution
Supply Voltage: 1V, Load: 1W
Grid Resistances: 0.5 Ω (ITRS 2012)
Load
Number
Power
of Loads
(W)
1
1
4
4
9
9
16
16
25
25
64
64
100
100
256
256
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Grid Power
(W)
0.13
0.67
1.69
3.57
7.02
23.76
49.32
169.4
Total
Power
(W)
1.13
4.67
10.69
19.57
32.02
87.76
149.32
425.4
ELEC 7770: Advanced36VLSI Design (Agrawal)
Efficiency
(%)
88.50
85.65
84.19
81.76
78.08
72.93
66.97
60.18
Low Voltage PDN Power Transfer
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ELEC 7770: Advanced37VLSI Design (Agrawal)
Low Voltage PDN Efficiency
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ELEC 7770: Advanced38VLSI Design (Agrawal)
Result: High Voltage Distribution
Supply Voltage: 3 V, Load: 1W
Grid Resistances: 0.5 Ω (ITRS 2012)
DC-DC Converter: LTC 3411-A Linear Technology, 100% Efficiency
Load
Total
H-V PDN
Number
Grid Power
Power
Power
Efficiency
of Loads
(W)
(W)
(W)
(%)
1
1
0.01
1.01
98.58
4
4
0.07
4.07
98.17
9
9
0.19
9.19
97.96
16
16
0.40
16.40
97.58
25
25
0.78
25.78
96.97
64
64
2.64
66.64
96.04
100
100
5.48
105.48
94.80
256
256
18.82
274.82
93.15
Spring 2016, Mar 28 . . .
ELEC 7770: Advanced39VLSI Design (Agrawal)
High Voltage PDN Power Transfer
Spring 2016, Mar 28 . . .
ELEC 7770: Advanced40VLSI Design (Agrawal)
High Voltage PDN Efficiency
Spring 2016, Mar 28 . . .
ELEC 7770: Advanced41VLSI Design (Agrawal)
Result: High Voltage Distribution
Supply Voltage: 3 V, Load: 1W
Grid Resistances: 0.5 Ω (ITRS 2012)
DC-DC Converter: LTC 3411-A Linear Technology, 80% Efficiency
Load
Total
Number
Power Grid Power Power
Efficiency (%)
of Loads
(W)
(W)
(W)
1
1
0.02
1.02
98.04
4
4
0.11
4.11
97.32
9
9
0.39
9.39
95.85
16
16
1.21
17.21
92.97
25
25
2.68
27.68
90.32
64
64
9.12
73.12
87.53
100
100
18.97
118.97
84.05
256
256
63.3
319.3
80.18
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High Voltage PDN Power Transfer
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ELEC 7770: Advanced43VLSI Design (Agrawal)
High Voltage PDN Efficiency
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Comparing Grid Power Loss
Number Load Power
of Loads
(W)
1
4
9
16
25
64
100
256
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1
4
9
16
25
64
100
256
PDN Grid Power Loss (W)
High-Voltage High-Voltage
Low(100% Eff.
(80% Eff.
Voltage
Converter) Converter)
PDN
0.13
0.01
0.02
0.67
0.07
0.11
1.69
0.19
0.39
3.57
0.40
1.21
7.02
0.78
2.68
23.76
2.64
9.12
49.32
5.48
18.97
169.40
18.82
63.3
ELEC 7770: Advanced45VLSI Design (Agrawal)
Comparing Grid Power Loss
Spring 2016, Mar 28 . . .
ELEC 7770: Advanced46VLSI Design (Agrawal)
Comparing PDN Efficiency
Number of
Loads
1
4
9
16
25
64
100
256
Spring 2016, Mar 28 . . .
Grid Efficiency (%)
High-Voltage
High-Voltage
PDN
PDN
Low-Voltage
(100% Eff.
(80% Eff.
PDN
Converter)
Converter)
88.50
98.58
98.04
85.65
98.17
97.32
84.19
97.96
95.85
81.76
97.58
92.97
78.08
96.97
90.32
72.93
96.04
87.53
66.97
94.80
84.05
60.18
93.15
80.18
ELEC 7770: Advanced47VLSI Design (Agrawal)
Comparing PDN Efficiencies
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ELEC 7770: Advanced48VLSI Design (Agrawal)
Challenges
 DC-DC Converter Design:
Efficiency
Power
Area
Output Drive Capacity
Fabrication
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ELEC 7770: Advanced49VLSI Design (Agrawal)
Reported Developments
Input Voltage: 3.3 V
Output Voltage: 1.3 V – 1.6 V
Output Drive Current: 26 mA
Efficiency: 75% - 87%
 Input Voltage: 3.6 V & 5.4 V
Output Voltage: 0.9 V
Output Drive Current: 250 mA
Efficiency: 87.8% & 79.6%
Sources:
B. Maity et al., Journal of Low Power Electronics 2012
V. Kursun et al., Multi-voltage CMOS Circuit Design. Wiley, 2006
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ELEC 7770: Advanced50VLSI Design (Agrawal)
Future Work





Have the capability of driving output loads of reasonable size
Have power efficiency of 90% or higher
Meet the tight area requirements of modern high-density ICs
Be fabricated on chip as a part of the SoC
Have ‘regulator’ capability to convert a range of input voltage
to the designated output voltage
DC-DC Converters
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ELEC 7770: Advanced51VLSI Design (Agrawal)
References
 D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC and Custom: Tools








and Techniques for Low Power Design. Springer, 2007.
M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual
for System-on-Chip Design. Springer, 2007.
V. Kursun and E. Friedman, Multivoltage CMOS Circuit Design. Wiley, 2006.
C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and
Process Compensation Over Different Technology Generations," Proc. International
Symp. Low Power Electronics and Design, 2003, pp. 116-121.
B. C. Paul, A. Agarwal, and K. Roy, "Low-Power Design Techniques for Scaled
Technologies,“ Integration, the VLSI Journal, vol. 39, no. 2, pp. 64-89, 2006.
"Linear Technology: LT3411A DC-DC Converter Demo Circuit @ONLINE,“ Nov. 2011.
M. Pedram and J. M. Rabaey, Power Aware Design Methodologies. Springer, 2002.
M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, “On-Chip Power Distribution
Grids with Multiple Supply Voltages for High-Performance Integrated Circuits," IEEE
Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp. 908-921, 2008.
Q. K. Zhu, Power Distribution Network Design for VLSI. Wiley-Interscience, 2004.
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ELEC 7770: Advanced52VLSI Design (Agrawal)