ELEC 7770
Advanced VLSI Design
Spring 2014
Gate Delay and Circuit Timing
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr16/course.html
Spring 2016, Feb 1 . .
ELEC 7770: Advanced VLSI Design (Agrawal)
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Delay of a Transition
Ron
VDD
ic(t)
vi (t)
vo(t)
CL
R = large
Ground
CL =
Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Charging of a Capacitor
R = Ron
t=0
v(t)
i(t)
C = CL
VDD
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
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=
dq(t)/dt
ELEC2200-002 Lecture 8
3
i(t)
=
C dv(t)/dt =
dv(t)
∫ ───── =
VDD – v(t)
ln [VDD – v(t)] =
[VDD – v(t)] /R
dt
∫ ────
RC
–t
── +
RC
A
Initial condition, t = 0, v(t) = 0 → A = ln VDD
–t
v(t) = VDD [1 – exp(───)] = 0.5VDD
RC
t = 0.69 RC
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
4
Delay: Definitions
 Rise time is the time a signal takes to rise from 10% to 90% of its
peak value.
 Fall time is the time a signal takes to drop from 90% to 10% of its
peak value.
 Delay of a gate or circuit is the time interval between the input
crossing 50% of peak value and the output crossing 50% of peak
value.
VDD
90% VDD
A
Fall time
10% VDD
GND
1→0
A
NOT
gate
Time
B
0→1
Gate delay
VDD
90% VDD
B
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10% VDD
GND
ELEC2200-002 Lecture 8
Rise time
Time
5
Inverter: Idealized Input
INPUT
VDD
GND
Gate delay
OUTPUT
VDD
0.5VDD
GND
Fall 2015, Nov 30
time
t =0
0.69CR
ELEC2200-002 Lecture 8
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Timing of a Digital Circuit
 Most digital circuits are clocked synchronous
finite state machines (FSM).
Primary
Inputs
FF
FF
FF
Combinational circuit
(Gates interconnected
without feedback)
Primary
Outputs
FF
Clock
FF
FF
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Timing Paths
Input
Signal
changes
Transient
region
Comb.
logic
Synchronized
With clock
Outputs
Inputs
Output
Observation
instant
time
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ELEC 7770: Advanced VLSI Design (Agrawal)
Clock period
8
Timing Analysis and Optimization
 Timing analysis
 Dynamic analysis: Simulation.
 Static timing analysis (STA): Vector-less topological analysis of
circuit.
 Timing optimization

 Performance
 Clock design
Other forms of design optimization
 Chip area
 Testability
 Power
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Circuit Delays
 Switching or inertial delay is the interval between input
change and output change of a gate:
 Depends on input capacitance, device (transistor)


characteristics and output capacitance of gate.
Also depends on input rise or fall times and states of other
inputs (second-order effects).
Approximation: fixed rise and fall delays (or min-max delay
range, or single fixed delay) for gate output.
 Propagation or interconnect delay is the time a transition
takes to travel between gates:
 Depends on transmission line effects (distributed R, L, C

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parameters, length and loading) of routing paths.
Approximation: modeled as lumped delays for gate inputs.
ELEC 7770: Advanced VLSI Design (Agrawal)
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Spice
 Circuit/device level analysis
 Circuit modeled as network of transistors, capacitors,
resistors and voltage/current sources.
 Node current equations using Kirchhoff’s current law.
 Analysis is accurate but expensive

 Used to characterize parts of a larger circuit.
Original references:
 L. W. Nagel and D. O. Pederson, “SPICE – Simulation
Program With Integrated Circuit Emphasis,” Memo ERLM382, EECS Dept., University of California, Berkeley, Apr.
1973.
 L. W. Nagel, SPICE 2, A Computer program to Simulate
Semiconductor Circuits, PhD Dissertation, University of
California, Berkeley, May 1975.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Logic Model of MOS Circuit
pMOS FETs
VDD
a
a
Ca
c
Cc
b
Cb nMOS
FETs
Cd
Ca , Cb , Cc and Cd are
node capacitances
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b
Da
c
Dc
Db
Da and Db are
interconnect or
propagation delays
Dc is inertial delay
of gate
ELEC 7770: Advanced VLSI Design (Agrawal)
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Spice Characterization
Input data pattern
Delay (ps)
Dynamic energy (pJ)
a=b=0→1
69
1.55
a = 1, b = 0 → 1
62
1.67
a = 0 → 1, b = 1
50
1.72
a=b=1→0
35
1.82
a = 1, b = 1 → 0
76
1.39
a = 1 → 0, b = 1
57
1.94
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Spice Characterization (Cont.)
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Input data pattern
Static power (pW)
a=b=0
5.05
a = 0, b = 1
13.1
a = 1, b = 0
5.10
a=b=1
28.5
ELEC 7770: Advanced VLSI Design (Agrawal)
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Complex Gates: Switch-Level Partitions
 Circuit partitioned into channel-connected components for Spice
characterization.
 Reference: R. E. Bryant, “A Switch-Level Model and Simulator for
MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp.
160-177, Feb. 1984.
Internal
switching
nodes not
seen by
logic
simulator
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G2
G1
G3
ELEC 7770: Advanced VLSI Design (Agrawal)
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Interconnect Delay: Elmore Delay Model
 W. Elmore, “The Transient Response of Damped Linear Networks with
Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19,
no.1, pp. 55-63, Jan. 1948.
2
R2
C2
s
R1
1
4
R4
C1
C4
R3
3
Shared resistance:
R5
C3
R45 = R1 + R3
R15 = R1
R34 = R1 + R3
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5
C5
ELEC 7770: Advanced VLSI Design (Agrawal)
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Elmore Delay Formula
N
Delay at node k = 0.69 Σ Cj × Rjk
j=1
where N = number of capacitive nodes in the network
Example:
Delay at node 5 = 0.69 [ R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4
(R1+R3+R5)C5 ]
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
1 3
1
0
1
P2
0
0
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2 4 6
3
2
P3
2
5
ELEC 7770: Advanced VLSI Design (Agrawal)
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Circuit Outputs
 Each path can potentially produce one signal

transition at the output.
The location of an output transition in time is
determined by the delay of the path.
Clock period
Final value
Initial value
Slow transitions
Fast transitions
time
Initial value
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Final value
ELEC 7770: Advanced VLSI Design (Agrawal)
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Delay and Discrete-Event Simulation
Inputs
(NAND gate)
Transient
region
a
b
c (CMOS)
Logic simulation
c (zero delay)
c (unit delay)
X
c (multiple delay)
Unknown (X)
c (minmax delay)
0
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ELEC 7770: Advanced VLSI Design (Agrawal)
rise=5, fall=5
min =2, max =5
Time units
20
Event-Driven Simulation
(Example)
a =1
c =1→0
e =1
g =1
2
2
d=0
4
b =1
f =0
Time stack
2
Scheduled
events
t=0
1
2
3
4
5
6
7
8
Activity
list
c=0
d, e
d = 1, e = 0
f, g
g=0
f=1
g
g=1
g
0
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4
8
Time, t
ELEC 7770: Advanced VLSI Design (Agrawal)
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Time Wheel (Circular Stack)
Current
time
pointer
max
t=0
1
Event link-list
2
3
4
5
6
7
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Timing Design and Delay Test
 Timing simulation:
 Critical paths are identified by static (vector-less)
timing analysis tools like Primetime (Synopsys).
 Timing or circuit-level simulation using designergenerated functional vectors verifies the design.
 Layout optimization: Critical path data are used in

placement and routing. Delay parameter
extraction, timing simulation and layout are
repeated for iterative improvement.
Testing: Some form of at-speed test is necessary.
Critical paths and all gate transition delays are
tested.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Static Timing Analysis (STA)
 Finds maximum and minimum delays between
Flip-flops
Combinational
circuit
Flip-flops
Flip-flops
all clocked flip-flops.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Early References
 T. I. Kirkpatrick and N. R. Clark, “PERT as an


Aid to Logic Design,” IBM J. Res. Dev., vol. 10,
no. 2, pp. 135-141, March 1966.
R. B. Hitchcock, Sr., “Timing Verification and the
Timing Analysis Program,” Proc. 19th Design
Automation Conf., 1982, pp. 594-604.
V. D. Agrawal, “Synchronous Path Analysis in
MOS Circuit Simulator,” Proc. 19th Design
Automation Conf., 1982, pp. 629-635.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Basic Ideas
 Adopted from project management
 Frederick W. Taylor (1856-1915)
 Henry Gantt (1861-1919)
 PERT – Program Evaluation and Review
Technique
 CPM – Critical Path Method
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ELEC 7770: Advanced VLSI Design (Agrawal)
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A Gantt Chart in Microsoft Excel
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Using a Gantt Chart
 Track progress of subtasks and project.
 Assess resource needs as a function of time.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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PERT (Program Evaluation and Review
Technique) Chart
Milestones
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Activities
ELEC 7770: Advanced VLSI Design (Agrawal)
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Example: Thesis Research
Begin
Defense
done
Analysis
completed
2, 4, 6 weeks
4, 5, 6
Problem
selected
3, 4, 5
minimum
average
maximum
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2, 3, 4
4, 4, 4
Thesis
Draft
done
Background
study
completed
5, 7, 9
Program
and
Experiment
completed
1, 2, 3
4, 4, 4
2, 4, 6
ELEC 7770: Advanced VLSI Design (Agrawal)
2, 2, 2
Thesis
submitted
1,2,3
Draft
revisions
30
Critical Path
Critical path is path of maximum average delay (26 weeks).
Begin
Defense
done
Analysis
completed
2, 4, 6 weeks
4, 5, 6
Problem
selected
3, 4, 5
minimum
average
maximum
Spring 2016, Feb 1 . .
2, 3, 4
4, 4, 4
Thesis
Draft
done
Background
study
completed
5, 7, 9
Program
and
Experiment
completed
1, 2, 3
4, 4, 4
2, 4, 6
ELEC 7770: Advanced VLSI Design (Agrawal)
2, 2, 2
Thesis
submitted
1,2,3
Draft
revisions
31
Timing Analysis Using PERT
H. Chang and S. S. Sapatnekar, “Statistical Timing Analysis
Considering Spatial Correlations Using a Single PERT_Like
Traversal,” Proc. International Conf. on Computer-Aided
Design, 2003, pp. 621-625.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Large Circuit Timing Analysis
 Determine gate delays:
 From layout analysis, or use approximate delays:
 Gate delay increases in proportion to number of
fanouts (increased capacitance)
 Delay decreases in proportion to increase in gate size
(reduced transistor channel resistance)
 Purpose of analysis is to verify timing behavior –

determine maximum speed of operation.
Methods of analysis:
 Circuit simulation – most accurate, expensive (Spice program)
 Static timing analysis (STA) – most efficient, approximate
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Static Timing Analysis (STA)
 Combinational logic for critical path delays.
 Circuit represented as an acyclic directed graph


(DAG).
Gates characterized by delays; gate function
ignored.
No inputs are used – worst-case analysis –
static analysis (simulation would be dynamic).
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Combinational Circuit of an FSM
A
1
H
1
Gate delay
B
1
E
4
G
1
Fanout
=4
C
2
F
2
J
1
D
1
Input to Output delay must not exceed clock period
Fall 2015, Nov 30
ELEC2200-002 Lecture 8
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Static Timing Analysis (STA) Step 1
Levelize circuit. Initialize arrival times at primary inputs to 0.
0
0
0
0
0
0
0
0
Level 0
Fall 2015, Nov 30
A
1
B
1
H
1
E
4
G
1
C
2
F
2
D
1
1
J
1
Level of a gate is one greater than
the maximum of fanin gate levels
2
3
ELEC2200-002 Lecture 8
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5
36
Static Timing Analysis (STA) Step 2
Determine output arrival times of gates in level order.
0
0
0
0
0
0
0
0
Level 0
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1
A
1
B
1
1
E
4
C
2
6
1
G
1
9
J
1
9
2
F
2
D
1
10
H
1
1
8
Arrival time at a gate output
= maximum of input arrivals + gate delay
2
3
ELEC2200-002 Lecture 8
4
5
37
Static Timing Analysis (STA) Step 3
Trace critical paths from the output with longest arrival time.
0
0
0
0
0
0
0
0
Level 0
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1
A
1
B
1
1
E
4
C
2
6
1
9
G
1
2
F
2
D
1
10
H
1
1
9
J
1
8
Critical path: C, E, F, G, H; delay = 10
2
3
ELEC2200-002 Lecture 8
4
5
38
Characteristics of STA
 Linear time analysis, Complexity is O(n), n is

number of gates and interconnects.
Variations:
 Find k longest paths:
 S. Kundu, “An Incremental Algorithm for Identification of
Longest (Shortest) Paths,” Integration, the VLSI Journal, vol.
17, no. 1, pp. 25-35, August 1994.
 Find worst-case delays from an input to all outputs.
 Linear programming methods.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Algorithms for Directed Acyclic Graphs
(DAG)
 Graph size: n = |V| + |E|, for |V| vertices and |E|




edges.
Levelization: O(n) (linear-time) algorithm finds
the maximum (or minimum) depth.
Path counting: O(n2) algorithm. Number of paths
can be exponential in n.
Finding all paths: Exponential-time algorithm.
Shortest (or longest) path between two nodes:
 Dijkstra’s algorithm: O(n2)
 Bellman-Ford algorithm: O(n3)
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References
 Delay modeling, simulation and testing:
 M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000.
 Analysis and Design:
 G. De Micheli, Synthesis and Optimization of Digital Circuits,
McGraw-Hill, 1994.
 N. Maheshwari and S. S. Sapatnekar, Timing Analysis and
Optimization of Sequential Circuits, Springer, 1999.
 PrimeTime (Static timing analysis tool):
 H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition,
Springer, 2002
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