ELEC 7770: Advanced VLSI Design
Spring 2014
Model-Based and Alternate Tests
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14
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Analog Test
 Analog circuits
 Analog circuit test methods
 Specification-based testing
 Direct measurement
 DSP-based testing
 Fault model based testing
 Alternate Test
 Summary
 References
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Analog Circuits









Operational amplifier (analog)
Programmable gain amplifier (mixed-signal)
Filters, active and passive (analog)
Comparator (mixed-signal)
Voltage regulator (analog or mixed-signal)
Analog mixer (analog)
Analog switches (analog)
Analog to digital converter (mixed-signal)
Digital to analog converter (mixed-signal)
 Phase locked loop (PLL) (mixed-signal)
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Test Parameters
 DC
 Continuity
 Leakage current
 Reference voltage
 Impedance
 Gain
 Power supply – sensitivity, common mode
rejection
 AC
 Gain – frequency and phase response
 Distortion – harmonic, intermodulation,
nonlinearity, crosstalk
 Noise – SNR, noise figure
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Analog Test (Traditional)
DC
~
Filter
RMS
Analog device
under test
(DUT)
PEAK
DC
ETC.
ETC.
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Stimulus
Response
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DSP-Based Mixed-Signal Test
Synthesizer
RAM D/A
Send
memory
Digitizer
Analog
Analog
Mixed-signal
device under
test (DUT)
Digital
Digital
A/D
RAM
Receive
memory
Synchronization
Vectors
Digital signal processor (DSP)
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Vectors
6
Waveform Synthesizer
© 1987 IEEE
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Waveform Digitizer
© 1987 IEEE
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Circuit Specification
Key Performance Specifications: TLC7524C
8-bit Multiplying Digital-to-Analog Converter
Resolution
8 Bits
Linearity error
½ LSB Max
Power dissipation at VDD = 5 V
5 mW Max
Settling time
100 ns Max
Propagation delay time
80 ns Max
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Voltage Mode Operation
REF
VO
R
R
R
RFB
2R
2R
2R
2R
2R
R
0
1
CS
0
1
0
1
0
Data Latches
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DB6
DB5
Data Inputs
VI
OUT1
OUT2
GND
WR
DB7
(MSB)
1
DB0
(LSB)
ELEC 7770: Advanced VLSI Design
VO = VI (D/256)
VDD = 5 V
OUT1 = 2.5 V
OUT2 = GND
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Operational/Timing Spec.
Parameter
Test conditions
For VDD = 5 V
±0.5 LSB
Linearity error
Gain error
Measured using the internal
feedback resistor. Normal full scale
range (FSR) = Vref – 1 LSB
±2.5 LSB
Settling time to ½ LSB
OUT1 load = 100 Ω,
Cext = 13 pF, etc.
100 ns
Prop. Delay, digital input to
90% final output current
CS
WR
tsu(CS) ≥ 40 ns
80 ns
th(CS) ≥ 0 ns
tw(WR) ≥ 40 ns
tsu(D) ≥ 25 ns
th(D) ≥ 10 ns
DB0-DB7
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Operating Range Spec.
Supply voltage, VDD
-0.3 V to 16.5 V
Digital input voltage range
-0.3 V to VDD+0.3 V
Reference voltage, Vref
±25 V
Peak digital input current
10μA
Operating temperature
-25ºC to 85ºC
Storage temperature
-65ºC to 150ºC
Case temperature for 10 s
260ºC
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Test Plan: Hardware Setup
+Full-scale code
D7-D0
DACOUT
Vref
2.5 V
+
RLOAD
1 kΩ
VM
+
Vout
-
-
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Test Program Pseudocode
dac_full_scale_voltage()
{
set VI1 = 2.5 V; /* Set the DAC voltage reference to 2.5 V */
start digital pattern = “dac_full_scale”; /* Set DAC output to
+full scale (2.5 V) */
connect meter: DAC_OUT /* Connect voltmeter to DAC output */
fsout = read_meter(), /* Read voltage level at DAC_OUT pin */
test fsout; /* Compare the DAC full scale output to data sheet limit */
}
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Analog Fault Models
Low-pass
filter
amplifier
Op Amp
High-pass
filter
A1
A2
fC1
A3
A4
fC2
First stage gain
High-pass filter gain
High-pass filter cutoff frequency
Low-pass AC voltage gain
Low-pass DC voltage gain
Low-pass filter cutoff frequency
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R2 / R1
R3 and C1
C1 and R3
R4, R5 and C2
R4 and R5
C2 and R5
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Bipartite Graph of Circuit
Minimum set of
parameters to
be observed
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Method of ATPG Using Sensitivities
N. B. Hamida and B. Kaminska, “Analog Circuit Testing Based on
Sensitivity Computation and New Circuit Modeling,” Proc. ITC-1993.
 Compute analog circuit sensitivities
 Construct analog circuit bipartite graph
 From graph, find which O/P parameters

(performances) to measure to guarantee maximal
coverage of parametric faults
 Determine which O/P parameters are most
sensitive to which component faults
Evaluate test quality, add test points to complete the
analog fault coverage
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Sensitivity
 Sensitivity of a circuit parameter y to variation in
a component value x is,
S(x,y) = (∆y/y)/(∆x/x)
where ∆x is small
 For our example, a parameter y can be gain or
cutoff frequency and components are resistors
and capacitors.
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Sensitivity
 Simulate the circuit with all components at

nominal values.
Determine sensitivity of one parametercomponent pair at a time:
 Find the minimum component value deviation,
positive or negative, such that a measurable
performance parameter deviation is produced.
 Repeat for all parameter-component pairs.
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Sensitivity Matrix of Circuit
Numbers in orange show highest sensitivity for a component.
-0.91
0
0
0
0
0
R1
1
0
0
0
0
0
R2
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0
0.58
-0.91
0
0
0
C1
0
0.38
-0.89
0
0
0
R3
0
0
0
-0.96
-0.97
0
R4
0
0
0
0.48
-0.97
-0.88
R5
ELEC 7770: Advanced VLSI Design
0
0
0
-0.48
0
-0.91
C2
A1
A2
fc1
A3
A4
fc2
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Tolerance
 Tolerance of a parameter y with respect to
variation in a component value x is,
Range A ≤ ∆x/x ≤ B
such that y remains within specification. All
other components are assumed to have
nominal values.
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Tolerance Box: Single-Parameter
Variation
5% ≤
A1
5% ≤
5% ≤
A2
5% ≤
5% ≤
A4
5% ≤
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ΔR1
R1
ΔR2
R2
ΔR3
R3
ΔC1
C1
ΔR4
R4
ΔR5
R5
5% ≤
≤ 15.98%
fC1
≤ 14.10%
5% ≤
≤ 20.27% fC2
≤ 11.60%
5% ≤
5% ≤
≤ 15.00%
≤ 15.00%
5% ≤
A3
5% ≤
5% ≤
ELEC 7770: Advanced VLSI Design
ΔR3
R3
ΔC1
C1
ΔR5
R5
ΔC2
C2
ΔR4
R4
ΔR5
R5
ΔC2
C2
≤ 14.81%
≤ 15.20%
≤ 14.65%
≤ 13.96%
≤ 15.00%
≤ 35.00%
≤ 35.00%
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Weighted Bipartite Graph
Five tests
provide most
sensitive
measurement
of all components
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IEEE 1149.4 Standard
Analog Test Bus (ATB)
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Digital/Analog Interfaces
At any
time, only
1 analog
pin can be
stimulated
and only 1
analog pin
can be
read
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Summary
 DSP-based tester has:
 Waveform synthesizer
 Waveform digitizer
 High frequency clock with dividers for
synchronization
 Analog test methods
 Specification-based functional testing
 Model-based analog testing
 Analog test bus allows static analog tests of
mixed-signal devices
 Boundary scan is a prerequisite
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References on Analog Test
 A. Afshar, Principles of Semiconductor Network Testing, Boston:

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




Butterworth-Heinemann, 1995.
M. Burns and G. Roberts, Introduction to Mixed-Signal IC Test and
Measurement, New York: Oxford University Press, 2000.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for
Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer,
2000.
R. W. Liu, editor, Testing and Diagnosis of Analog Circuits and
Systems, New York: Van Nostrand Reinhold, 1991.
M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal
Circuits, Los Alamitos, California: IEEE Computer Society Press,
1987.
A. Osseiran, Analog and Mixed-Signal Boundary Scan, Boston:
Springer, 1999.
T. Ozawa, editor, Analog Methods for Computer-Aided Circuit
Analysis and Diagnosis, New York: Marcel Dekker, 1988.
B. Vinnakota, editor, Analog and Mixed-Signal Test, Upper Saddle
River, New Jersey: Prentice-Hall PTR, 1998.
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Setting Thresholds in Model-Based
Test
 In model-based test, component values are


determined.
Preset “thresholds” for component variation
classify the device under test as good or faulty.
How do we determine the “thresholds”. For
example,
 Circuit is good if R1’ ≤ R1 ≤ R1’’
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An Operational Amplifier
R2
R1
+
Gain = V2/V1 = R2/R1
V1
_
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V2
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Pessimism in Model-Based Test
Yield
loss
R2
Only good
devices
accepted
0
0
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R1
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Reducing Yield Loss
Reduced
yield loss
R2
Faulty
devices
accepted
0
0
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R1
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Yield Loss and Defect Level
 Yield loss: Amount of yield reduction because


some good devices fail non-functional tests.
Defect level (DL): Fraction of faulty devices
among those that pass non-functional tests.
Example: 1,0000 devices are fabricated. 7,000
are good. True yield, y = 0.7. Test passes 6,900
good and 150 bad devices. Then,
 Yield loss = (7,000 – 6,900)/10,000 = 0.01 or 1%
 DL = 150/(6,900+150) = 0.02128 or 2.128% or 21,280
DPM (defective parts per million)
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Yield Loss and Defect Level
All fabricated devices
Good
devices
Devices
passing
test
Yield
loss
Defect
level
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Component Variation (Statistical)
Uniform
Gaussian
Mean
Mean
Component (R or C) value
Component (R or C) value
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Monte Carlo Simulation
 Consider operational amplifier example.
 R1 and R2 are random variables with given (uniform
or Gaussian) probability density functions with
 Mean = nominal value
 Standard deviation based on manufacturing data
 Generate large number of samples for R1 and R2
 Simulate each sample using spice
 Determine gain for each sample
 For each set of tolerance limits, determine yield loss
and defect level.
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Monte Carlo Simulation Data
R2
0
0
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R1
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Setting Test Limits
Minimize yield loss
R2
Minimize defect level
0
0
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R1
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Alternate Test
 Besides components (e.g., R1 and R2 for



operational amplifier) easily measurable parameters
used for testing.
An example is the supply current IDD of the
operational amplifier.
A simple test is to measure IDD(0) for 0V input.
Monte Carlo simulation is then used to set the limits
on IDD(0).
 Large number of sample circuits with component
variations are simulated to determine thresholds for
IDD(0).
 Additional measurements can improve test.
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Alternate Test: Setting Thresholds
Minimize yield loss
Gain
Within
spec.
gain
Minimize defect level
Fail
Pass
Fail
0
0
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IDD(0)
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Zero Defect Level
Yield loss increased
Gain
Within
spec.
gain
Fail
Pass
Fail
0
0
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IDD(0)
ELEC 7770: Advanced VLSI Design
Zero defect level
40
Zero Yield Loss
Zero yield loss
Gain
Within
spec.
gain
Increased defect level
Fail
Pass
Fail
0
0
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IDD(0)
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References
 P. N. Variyam, S. Cherubal and A. Chatterjee,

“Prediction of Analog Performance Parameters
Using Fast Transient Testing,” IEEE Trans.
Computer-Aided Design, vol. 21, no. 3, pp. 349361, March 2002.
H.-G. Stratigopoulos and Y. Makris, “Error
Moderation in Low-Cost Machine-LearningBased Analog/RF Testing,” IEEE Trans.
Computer-Aided Design, vol. 27, no. 2, pp. 339351, February 2008.
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