ELEC 7770 Advanced VLSI Design Spring 2008 System Test

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ELEC 7770
Advanced VLSI Design
Spring 2008
System Test
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
1
A System and Its Testing
 A system is an organization of components


(hardware/software parts and subsystems) with
capability to perform useful functions.
Functional test verifies integrity of system:
 Checks for presence and sanity of subsystems
 Checks for system specifications
 Executes selected (critical) functions
Diagnostic test isolates faulty part:
 For field maintenance isolates lowest replaceable unit (LRU),
e.g., a board, disc drive, or I/O subsystem
 For shop repair isolates shop replaceable unit (SRU), e.g., a
faulty chip on a board
 Diagnostic resolution is the number of suspected faulty units
identified by test; fewer suspects mean higher resolution
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
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System Test Applications
Application
Functional test
Diagnostic test
Resolution
Manufacturing
Yes
LRU, SRU
Maintenance
Yes
A
Field repair
LRU
Shop repair
SRU
LRU: Lowest replaceable unit
SRU: Shop replaceable unit
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
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Functional Test
 All or selected (critical) operations executed



with non-exhaustive data.
Tests are a subset of design verification tests
(test-benches).
Software test metrics used: statement, branch
and path coverages; provide low (~70%)
structural hardware fault coverage.
Examples:
 Microprocessor test – all instructions with
random data (David, 1998).
 Instruction-set fault model – wrong instruction is
executed (Thatte and Abraham, IEEETC-1980).
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Gate-Level Diagnosis
Karnaugh map
Logic circuit
(shaded squares are true outputs)
b
a
b
c
d
T2
e
a
Stuck-at fault tests:
T1 = 010
T2 = 011
T3 = 100
T4 = 110
Spring 08, Apr 17
T1
ELEC 7770: Advanced VLSI Design (Agrawal)
T4
T3
c
5
Gate Replacement Fault
Karnaugh map
Faulty circuit
(faulty output:
Only red sqaure is 1 output)
(OR replaced by AND)
a
b
c
b
d
T2
e
a
Stuck-at fault tests:
T1 = 010 (pass)
T2 = 011 (fail)
T3 = 100 (pass)
T4 = 110 (fail)
Spring 08, Apr 17
T1
ELEC 7770: Advanced VLSI Design (Agrawal)
T4
T3
c
6
Bridging Fault
Faulty circuit
Karnaugh map
(OR bridge: a, c)
(all red squares are faulty 1 outputs)
b
a
a+c
b
c
d
T2
e
a+c
a
Stuck-at fault tests:
T1 = 010 (pass)
T2 = 011 (pass)
T3 = 100 (fail)
T4 = 110 (pass)
Spring 08, Apr 17
T1
ELEC 7770: Advanced VLSI Design (Agrawal)
T4
T3
c
7
Fault Dictionary
Fault
Test syndrome
t1
t2
t3
t4
No fault
0
0
0
0
a0, b0, d0
0
0
0
1
a1
1
0
0
0
b1
0
0
1
0
c0
0
1
0
0
c1, d1, e1
1
0
1
0
e0
0
1
0
1
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
a0 : Line a stuckat-0
ti = 0, if Ti passes
= 1, if Ti fails
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Diagnosis with Dictionary
Dictionary look-up with minimum Hamming distance
Fault
OR
Test syndrome
t1 t2 t3 t4
Diagnosis
AND
0
1
0
1
e0
OR-bridge (a,c)
0
0
1
0
b1
1
1
1
1
c1, d1, e1, e0
OR
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NOR
ELEC 7770: Advanced VLSI Design (Agrawal)
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Diagnostic Tree
T3
b1
T2
Pass: t4=0
Fail: t4=1
a1
T3
a1, c1, d1, e1
OR bridge
(a,c)
c1, d1, e1
a0, b0, d0
T2
a0, b0, d0, e0
Spring 08, Apr 17
c0
T1
T4
No fault
found
e0
OR
AND
OR
NOR
ELEC 7770: Advanced VLSI Design (Agrawal)
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System Test: A DFT Problem
 Changing scenario in VLSI:




Spring 08, Apr 17
Mixed-signal (analog and RF) circuits
System-on-a-chip
Multi-chip modules
Intellectual property (IP) cores
ELEC 7770: Advanced VLSI Design (Agrawal)
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Conventional Test:
In-Circuit Test (ICT)
 A bed-of-nails fixture provides direct access to each


chip on the board.
Advantages: Thorough test for devices; good
interconnect test.
Limitations:
 Works best when analog and digital functions are
implemented on separate chips.
 Devices must be designed for backdriving protection.
 Not applicable to system-on-a-chip (SOC).
 Disadvantages:
 High cost and inflexibility of test fixture.
 System test must check for timing.
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
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PCB vs. SOC
PCB






SOC
Tested parts
In-circuit test (ICT)
Easy test access
Bulky
Slow
High assembly cost
Spring 08, Apr 17






High reliability
Fast interconnects
Low cost
Untested cores
No internal test
access
Mixed-signal devices
ELEC 7770: Advanced VLSI Design (Agrawal)
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Core-Based Design
 Cores are predesigned and verified but
untested blocks:
 Soft core (synthesizable RTL)
 Firm core (gate-level netlist)
 Hard core (non-modifiable layout, often called
legacy core)
 Core is the intellectual property of vendor

(internal details not available to user.)
Core-vendor supplied tests must be applied
to embedded cores.
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
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Partitioning for Test
 Partition according to test methodology:
 Logic blocks
 Memory blocks
 Analog blocks
 Provide test access:
 Boundary scan
 Analog test bus
 Provide test-wrappers (also called collars)
for cores.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Test-Wrapper for a Core
 Test-wrapper (or collar) is the logic added around a

core to provide test access to the embedded core.
Test-wrapper provides:
 For each core input terminal
 A normal mode – Core terminal driven by host chip
 An external test mode – Wrapper element observes core
input terminal for interconnect test
 An internal test mode – Wrapper element controls state of
core input terminal for testing the logic inside core
 For each core output terminal
 A normal mode – Host chip driven by core terminal
 An external test mode – Host chip is driven by wrapper
element for interconnect test
 An internal test mode – Wrapper element observes core
outputs for core test
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ELEC 7770: Advanced VLSI Design (Agrawal)
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A Test-Wrapper
from/to
External
Test pins
Scan chain
to/from TAP
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
Functional
core outputs
Core
Scan chain
Scan chain
Functional
core inputs
Wrapper
elements
Wrapper
test
controller
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Overhead of Test Access
 Test access is non-intrusive.
 Hardware is added to each I/O signal of block


to be tested.
Test access interconnects are mostly local.
Hardware overhead is proportional to:
(Block area)
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– 1/2
ELEC 7770: Advanced VLSI Design (Agrawal)
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Overhead Estimate
Rent’s rule: For a logic block the number of gates G
and the number of terminals t are related by
t =KG
a
where 1 ≤ K ≤ 5, and a ~ 0.5.
Assume that block area A is proportional to G, i.e.,
t is proportional to A 0.5. Since test logic is added
to each terminal t,
Test logic added to terminals
–0.5
Overhead = ──────────────────── ~ A
A
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ELEC 7770: Advanced VLSI Design (Agrawal)
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DFT Architecture for SOC
Test
sink
User defined test access mechanism (TAM)
1
Functional
outputs
Module
N
wrapper
Module
Func.
outputs
Func.
inputs
Test
Test
Functional
inputs
wrapper
Test
source
Instruction register control
Spring 08, Apr 17
TDO
TRST
TMS
TDI
SOC inputs
TCK
Test access port (TAP)
Serial instruction data
ELEC 7770: Advanced VLSI Design (Agrawal)
SOC outputs
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DFT Components
 Test source: Provides test vectors via on-chip LFSR,



counter, ROM, or off-chip ATE.
Test sink: Provides output verification using on-chip
signature analyzer, or off-chip ATE.
Test access mechanism (TAM): User-defined test data
communication structure; carries test signals from
source to module, and module to sink; tests module
interconnects via test-wrappers; TAM may contain bus,
boundary-scan and analog test bus components.
Test controller: Boundary-scan test access port (TAP);
receives control signals from outside; serially loads
test instructions in test-wrappers.
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Summary
 Functional test: verify system hardware, software,


function and performance; pass/fail test with limited
diagnosis; high ( ~100%) software coverage metrics;
low ( ~70%) structural fault coverage.
Diagnostic test: High structural coverage; high
diagnostic resolution; procedures use fault dictionary
or diagnostic tree.
SOC design for testability:
 Partition SOC into blocks of logic, memory and analog




circuitry, often on architectural boundaries.
Provide external or built-in tests for blocks.
Provide test access via boundary scan and/or analog test
bus.
Develop interconnect tests and system functional tests.
Develop diagnostic procedures.
Spring 08, Apr 17
ELEC 7770: Advanced VLSI Design (Agrawal)
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