5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
TUTORIAL ON PRIMETIME PX
MRIDULA ALLANI
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
USING MODELSIM TO GENERATE VCD FILE
1. Save your VHDL and Verilog
files., including the testbench in
a folder.
3. File/New /Project
2. Click Windows Start-up
Button and go to
/Programs/ECE/Modelsim
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
USING MODELSIM TO GENERATE VCD FILE
2. Add existing VHDL or Verilog
files to the project.
1. Type the Project name
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
USING MODELSIM TO GENERATE VCD FILE
2. If the compilation is
successful, you will see a green
check mark beside your file and
a success message at the
bottom in the Modelsim
command prompt
1. Compile your VHDL or Verilog
files.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
USING MODELSIM TO GENERATE VCD FILE
1. Start simulation
2. Select the top-level module
(testbench)
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
USING MODELSIM TO GENERATE VCD FILE
1. Type the following commands at the Modelsim
command prompt (change according to your file
names, directory and run as long as your testbench
simulation lasts):
cd
//sage/homes/Documents/Synopsys_Tools/Project1
vlib work
vlog one_bit_adder.v ripple_adder.v tb_ripple_adder.v
# vcom one_bit_adder.vhd ripple_adder.vhd
tb_ripple_adder.vhd
vopt tb_ripple_adder +acc -o tb_ripple_adder_opt
vsim tb_ripple_adder_opt
vcd file ripple_adder_dump.vcd
vcd add /tb_ripple_adder/DUT/*
run 2000ns
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
STARTING SECURE CRT
1. Click Windows Start-up
Button and go to
/Programs/ECE/SecureCRT
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
STARTING SECURE CRT
3. Before connecting to the
session, go to session
properties , choose
Remote/X11 and check
Forward X11 packets.
1. Choose engineering session.
2. If ‘Engineering’ is
unavailable, start a new session
port.eng.auburn.edu
or
ettin.eng.auburn.edu
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
STARTING SECURE CRT
2. Connect anywhere (hit
‘Enter’ key) and type your
password again.
1. Type your username and
password.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
STARTING XWIN-32
1. Click Windows Start-up
Button and go to
/Programs/ECE/X-Win32 2010
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
STARTING XWIN-32
1. Go to ‘Window’ tab in the Xconfig window and select
‘Multiple’ windows option from
the drop-down.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SYNTHESIZING USING DESIGN COMPILER
2. Type ‘dc_shell ‘at the shell
prompt.
1. Save your
dotsynopsys_dc.setup file and
your design compiler
(dc_synScript.tcl) and
primetime (pt_script.tcl) scripts
in a folder.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SYNTHESIZING USING DESIGN COMPILER
1. Type
source dcsynScript.tcl
at the dc_shell command
prompt. Sample script for
design compiler will be found at
the class website.
2. Sample synthesized file.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
RUNNING PRIMETIME SCRIPT
2. Type ‘pt_shell’ at the x-term
window command prompt.
1. Type primetime at the shell
command prompt.
3. Type
source pt_script.tcl
at the pt_shell command prompt. Sample
script for primetime will be found at the
class website.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SAMPLE POWER REPORT
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
COMPONENTS OF POWER DISSIPATION
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Static Power
 Leakage Power = V * Ileak
Dynamic Power
 Switching Power
= ½ * Cload * V² * f
 Internal Power
= (½ * Cint * V² *f) + (V * Isc)
Cload = total load capacitance at the
cell output
f = rate of state transitions
Cint = internal load capacitance
ISC = short-circuit current
Iintsw = Internal switching current
Ileak = Leakage current
Isw = Switching current
A simple buffer cell
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
POWER ANALYSIS FLOWS IN PRIMETIME PX
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VCD file gives an event-based simulation activity.
SAIF file gives the toggle rates of the nets.
In case of vector-free analysis, the toggle rates are calculated using internal zero-delay
simulation.
Power analysis can be done at both gate-level and RTL-levels.
For RTL-level analysis, RTL-level VCD or SAIF files are used.
For gate-level analysis, gate-level VCD or SAIF files are used.
VCD-based analysis gives the most accurate results.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SOME USEFUL dc_shell COMMANDS
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
INVOKING DESIGN COMPILER
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dc_shell [-f script_file][-x command_string][-no_init][no_home_init][-no_local_init][-checkout feature_list][-64bit][wait wait_time][-timeout timeout_value][-version][-no_log]
-f script_file
Opens the script file containing dc_shell commands before
displaying dc_shell command prompt
-x command_string
Executes the dc_shell command contained in 'command_string'
-x 'command_string1'; 'command_string2';
Executes multiple dc_shell commands
-64bit
Executes dc_shell in 64-bit environment
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SETTING AREA CONSTRAINT
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set_max_area [-ignore_tns] area_value
-ignore_tns
Specifies area above total negative slack, i.e., the timing
violations might be ignored to maximize area.
area_value
Gives the maximum allowed area. Units should be same as
units used in the technology library
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SETTING DELAY CONSTRAINT
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set_max_delay delay_value [-rise | -fall] [-from from_list |-rise_from
rise_from_list | -fall_from fall_from_list][-through through_list] [rise_through rise_through_list][-fall_through fall_through_list][-to
to_list |-rise_to rise_to_list |-fall_to fall_to_list][-group_path
group_name][-reset_path]
delay_value
Specifies the maximum delay between start and end points. Units should match
the units used in the technology library.
-rise | -fall
If '-rise' or '-fall' is specified, then the rise and fall delays are not constrained
-from from_list
Specifies the start point for delay value. It can be a port, pin, clock, or cell name
-to to_list
Specifies the end point
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SETTING POWER CONSTRAINTS
set_max_dynamic_power dynamic_power
[GW | MW | KW | W | mW | uW | nW | pW | fW | aW]
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set_max_leakage_power leakage_power
[GW | MW | KW | W | mW | uW | nW | pW | fW | aW]
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set_max_total_power total_power
[GW | MW | KW | W | mW | uW | nW | pW | fW | aW]
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
COMPILE OPTIONS
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compile [-no_map][-map_effort medium | high][-area_effort
none | low | medium | high][-incremental_mapping][exact_map][-ungroup_all][-boundary_optimization][-auto_ungroup
area | delay][-no_design_rule | -only_design_rule | only_hold_time][-scan][-top][-power_effort none | low | medium |
high][-gate_clock]
-no_map
Does not map the design to the library cells
-map_effort medium | high
Defines the amount of CPU time spent in mapping libraries
-ungroup_all
Removes the hierarchy from the design
-top
Fixes all design rule violations
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
DEFINING CLOCK
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create_clock [-name clock_name][-add][source_objects][period period_value][-waveform edge_list]
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-name clock_name
Defines the name of the clock
-add
Used to define a new clock when using multiple clocks. If not used, the
command over writes the previous clock declaration.
source_objects
Defines the ports or pins to which the clock is applied.
-period period_value
Defines the period of the clock.
-waveform edge_list
Specifies the rise and fall times alternatively in clock cycle.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SPECIFYING THE OPERATING CONDITIONS
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create_operating_conditions -name name -library
library_name -process process_value -temperature
temperature_value -voltage voltage_value [-tree_type tree_type] [calc_mode calc_mode ][-rail_voltages rail_value_pairs]
-name name
Name of the new operating conditions
-library library_name
The library name
-process process_value
Process scaling factor 0.0 to 100.0 (float value)
-temperature temperature_value
Temperature values -300.0ºC to 500.0 ºC (float value)
-voltage voltage_value
Voltage value 0.0 10 1000.0 (float value)
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
GENERATING AREA REPORTS
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report_area [-nosplit] [-physical] [-hierarchy]
-nosplit
Reports design information in fixed-width columns
-physical
Reports the core area and aspect ratio of the design
-hierarchy
Reports area of all cells across hierarchy
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
GENERATING TIMING REPORT
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report_timing [-to to_list][-from from_list][-through through_list][-path
short | full | full_clock | full_clock_expanded | only | end][-delay min |
min_rise | min_fall | max | max_rise | max_fall][-nworst paths_per_endpoint][max_paths max_path_count][-input_pins][-nets][-transition_time][crosstalk_delta][-capacitance][-attributes][-physical][-slack_greater_than
greater_slack_limit][-slack_lesser_than lesser_slack_limit][-lesser_path
max_path_delay][-greater_path min_path_delay][-loops][-true [-true_threshold
path_delay]][-justify][-enable_preset_clear_arcs][-significant_digits digits][nosplit][-sort_by group | slack][-group group_name][-trace_latch_borrow][derate][-scenario scenario_list][-temperature][-voltage]
-to to_list
Reports paths going to the clocks, ports, pins listed
-from from_list
Reports paths starting from the listed clocks, pins and ports
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
GENERATING TIMING REPORT
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-through through_list
Reports the paths through the ports, pins or clocks listed
-path short | full | full_clock | full_clock_expanded | only | end
Specifies the way the delay path is reported
-slack_greater_than greater_slack_limit or -slack_lesser_than lesser_slack_limit
Reports paths that have slack greater than or less than the limit
-greater_path min_path_delay or -lesser_path max_path_delay
Reports paths that have delay greater than or less than the limit
-temperature
Reports the operating condition temperature for each path element.
-voltage
Reports the operating condition voltage for each path element.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
GENERATING POWER REPORT
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report_power [-net][-cell][-only cell_or_net_list][-hier][-hier_level
level_value][-verbose][-cumulative][-flat][-exclude_boundary_nets][include_input_nets][-analysis_effort low | medium | high][-nworst number][sort_mode mode][-histogram [-exclude_leq le_val | -exclude_geq ge_val]][nosplit][-scenario scenario_list]
-net
Reports power consumed by nets
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-cell
Reports power consumed by cells
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-only cell_or_net_list
Reports power consumed by listed cell or net
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-hier
Reports power in hierarchical format
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-include_input_nets
Includes the power consumed by primary input nets
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-analysis_effort low | medium | high
Specifies the accuracy of estimating the switching activity used in power estimate.
This statement trades off accuracy with runtime
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-histogram [-exclude_leq le_val | -exclude_geq ge_val]
Reports power consumed by each net in histogram format within the range falling
between 'le_val' and 'ge_val'
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
OTHER COMMANDS…
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quit or exit
Terminates the dc_shell command prompt
Ctrl+C
Cancels current command
Command -help
Arguments related to the command are listed
Command > my_file
Directs the output of the command to the file 'my_file'
Command >> my_file
Appends the command output at the end of the contents of
'my_file'
history
Displays the commands used in a dc_shell session
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SOME USEFUL pt_shell COMMANDS
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
INVOKING PRIMETIME
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pt_shell [-f file_name] [-gui] [-display display_env_var] [-x
command_string] [-no_init] [-version]s tring file_name string
display_env_var string command_string
-32bit or -64bit
Specifies whether to use 32-bit or 64-bit executable files.
-f file_name
Executes the file before displaying the pt_shell command prompt.
-gui
Starts the GUI.
-no_init
Prevents execution of .synopsys_pt.setup startup files.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
CHECKING POWER AND TIMING
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check_power [-verbose][-significant_digits digits][override_defaults check_list][-include check_list][-exclude check_list]
check_timing [-verbose] [-significant_digits digits] [ms_min_separation delta][-override_defaults check_list][-include
check_list][-exclude check_list]
-verbose
Shows detailed information about potential problems.
-significant_digits digits
Specifies the precision of the results.
check_list
It lists the checks to be performed.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
SPECIFYING THE OPERATING CONDITIONS
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create_operating_conditions -name name -library library_name process process_value -temperature temperature_value -voltage
voltage_value [-tree_type tree_type][-calc_mode calc_mode][-rail_voltages
rail_value_pairs]
-name name
Name of the new operating conditions
-library library_name
The library name
-process process_value
Process scaling factor 0.0 to 100.0 (float value)
-temperature temperature_value
Temperature values -300.0ºC to 500.0 ºC (float value)
-voltage voltage_value
Voltage value 0.0 10 1000.0 (float value)
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
READING ACTIVITY FILES
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read_saif file_name [-strip_path prefix] [-path prefix][-ignore ignore_name][exclude exclude_file_name][-derate_glitch value][-quiet]
file_name
Gives the SAIF file name.
-strip_path prefix
The read_saif command assumes that the current design is instantiated as an instance in
the testbench used to generate the SAIF file. The current design, therefore, appears as an
instance in the SAIF file. The -strip_path argument specifies the name of the
instance of
the current design as it appears in the SAIF file.
-ignore ignore_name
Specifies the name of an instance in the SAIF file for which switching activity is to be
ignored.
-exclude exclude_file_name
Specifies the files whose switching activity is to be ignored.
-quiet
Suppresses the warnings.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
READING ACTIVITY FILES
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read_vcd [-path prefix][-strip_path prefix][-zero_delay][-pipe_exec
command][-cells cell_list][-time time_list] file_name
-path prefix
Gives the relative path from the given design to the low-level design for which VCD file has
been created.
-strip_path prefix
The read_saif command assumes that the current design is instantiated as an instance in
the testbench used to generate the SAIF file. The current design, therefore, appears as
an instance in the SAIF file. The -strip_path argument specifies the name of the instance of
the current design as it appears in the SAIF file.
-zero_delay
Specifies that the VCD file has been generated from a zero-delay simulation.
-pipe_exec command
Generates the VCD file and directly supplies it to Primetime PX.
-time time_window_value
Gives the time in ns for which the power has to be calculated.
-cells cell_list
Lists the cells for which the power has to be calculated.
file_name
Gives the VCD file name.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
GENERATING POWER REPORT
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report_power [-net_power][-cell_power][-leaf][-include_boundary_nets][include_estimated_clock_network][-sort_by sort_method][-nworst number][power_greater_than threshold][-hierarchy][-levels level][-clocks clock_list][groups group_list][-leakage_only][-no_propagation][object_list][-verbose][nosplit][-variation_quantile quantile]
-net_power
Reports net-based power
-cell_power
Reports cell-based power
-only cell_or_net_list
Reports power consumed by listed cell or net
-include_boundary_nets
Includes the power consumed by primary input nets
-power_greater_than threshold
Reports total power consumed greater than a given threshold
-hierarchy
Generates hierarchy-based power report
-leakage_only
Reports leakage power only
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
GENERATING POWER REPORT
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create_power_waveforms [-output file_name][-format
file_format][-interval sampling_interval][-leaf][-levels level][groups group_list][-clocks clock_list][-cycle_accurate][cycle_accurate_clock clock_name][cycle_accurate_cycle_count num_cycles][object_list]
-output file_name
Specify the prefix of the file in which the waveform data is to be written.
-format file_format
Specify the format of the file in which the waveform data is to be written.(fsdb)
-interval sampling_interval
Specify the sampling interval that is used for power waveform.
-leaf
Indicates that waveforms for leaf cells are to be created as well. By default,
waveforms are not created for leaf cells.
-clocks clock_list
This option is only used when generating average cycle waveform in the SAIF or
Vector Free flow. Specifies the clocks based on which average waveform is to
be created.
object_list
Create power waveforms only for the specified cells.
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5270/6270 Guest Lecture: M. Allani
Spr 2011, Mar 28 . . .
REFERENCES
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Synthesis with script files, Dr. Nelson’s CAD Tools Course Slides
http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/
Virginia Tech VLSI Design Tutorials
http://www.vtvt.ece.vt.edu/vlsidesign/tutorialSynopsys.php
Introduction to VHDL, Dr. Agrawal’s Digital Logic Circuits Course Slides
http://www.eng.auburn.edu/~agrawvd/COURSE/E2200_Fall10/course.html
Design Compiler User Guide
Primetime PX User Guide
Design Compiler Command Reference
Primetime PX Command Reference
Other Synopsys Documentation
http://www.synopsys.com/Tools/Implementation/SignOff/CapsuleModule/
ptpx_wp.pdf
http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime
.aspx
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