Introduction to Computing Systems
from bits & gates to C & beyond
Chapter 3
Digital Logic Structures
Transistors
 Logic gates & Boolean logic
 Combinational logic
 Storage Elements
 Memory

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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Transistors

An electronic switch
like light switch or faucet
switches between insulator and conductor
switch is closed (conducts) between A & B
depending on the voltage on G (gate)
Open switch:
no current flows
3-2
Closed switch:
current flows
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CMOS Transistors

CMOS
= Complementary Metal-Oxide Semiconductor
Standard type for digital applications
Two types: N (negative) and P (positive)
N and P transistors operate in inverse modes
A
A
P
G
G
A
B
Open if gate is “on”
Closed if gate isB“off”
3-3
N
G
B
Closed if gate is “on”
Open if gate is “off”
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Inverter Gate
2.9 v
P
In
Out
N
0v
3-4
In Out
0 1
1 0
 When the input is on (In =
high voltage), the P-type
transistor is open and the Ntype is closed, so the output
is off (Out = low voltage).
 Vice-versa: when the Input is
off (In = low voltage), the
output is connected to the
high voltage.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
NOR Gate
2.9 v
P
A
P
B
C
N
N
0v
0v
3-5
A
0
0
1
1
B
0
1
0
1
C
1
0
0
0
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
NOR Gate - Operation
2.9 v
2.9 v
2.9 v
0v
2.9 v
P
0v
P
2.9 v
P
P
0v
2.9 v
2.9 v
P
P
0v
0v
N
N
N
N
N
N
0v
0v
3-6
0v
0v
0v
0v
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
OR Gate
= a NOR gate followed by an inverter
A
B
3-7
C
D
A
0
0
1
1
B
0
1
0
1
C
1
0
0
0
D
0
1
1
1
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NAND & AND Gates
A
B
C
3-8
D
A
0
0
1
1
B
0
1
0
1
C
1
1
1
0
D
0
0
0
1
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Logic Gates & Symbols
Inverter (=NOT)
a
inverts 0 to 1
and 1 to 0
b
a
c
b
a
c
c
b
AND gate
OR gate
c is 1 only if both
a and b are 1
c is 1 if either
a or b is 1
a
b
NAND gate
NOR gate
c is 0 only if both
a and b are 1
c is 0 if either
a or b are 1
c
Note: gates can have more than two inputs.
3-9
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De Morgan’s Law

A and B = not((not A) or (not B))
A and B  A or B

A or B = not((not A) and (not B))
A or B  A and B

=
=
Completeness
 AND, OR and NOT are sufficient to represent any truth table.
 Actually: AND & NOT, or OR & NOT are separately sufficient.
 So: all we need are NOR or NAND gates.
3 - 10
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Representation of Logic Functions

A logic function can be represented as
 a truth table
 a logic expression
 a logic circuit

Example
f  a.(b.c  d)  a.c  a.b.c  a.d  a.c
a
b
c
d
3 - 11
f
a
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
c
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
f
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
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Types of Logic Structures
Two types of logic structures (devices)
 Storage structures: permit the storage of information (1 bit).
 Decision structures: can make a decision but do not remember what it
was: gates belong to this category.
Combinational logic
 a logic structure is combinational if it is constructed from decision
elements only: gates or other combinational logic structures.
 the output of a combinational logic structure depends strictly on its
current input.
Three examples
 Decoder
 Multiplexer (MUX)
 Full adder
3 - 12
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Decoder
A
B
i=0
i=1
i=2
i=3
3 - 13
1, iff A,B is 00
1, iff A,B is 01
 An n input decoder has 2n
outputs.
 Outputi is 1 iff the binary
value of the n-bit input is i.
1, iff A,B is 10
1, iff A,B is 11
 At any time, exactly one
output is 1, all others are 0.
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
Multiplexer (MUX)
A
B
C
D
S0  In general, a MUX has
 2n data inputs
S1
 n select (or control) lines
 and 1 output.
 It behaves like a channel selector.
Out  A. S0 . S1  B. S0 .S1  C.S0 . S1  D.S0 .S1
A
Out
A 4-to-1 MUX:
Out takes the value of A,B, C or D
depending on the value of S (00, 01, 10, 11)
3 - 14
B
C
D
S[1:0]
Out
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Adder
Half
Adder
 2 inputs
 2 outputs: sum and carry
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
S
0
1
1
0
Half-adder truth table
Full
Adder
 performs the addition in column i
 3 inputs: ai, bi and ci
 2 outputs: si and ci+1
 ci is the carry in from bit position i-1
 ci+1 is the carry out to bit position i+1
3 - 15
c n1 c n2 ... c 1 0
 a n1 a n2 ... a1 a 0
 b n1 b n2 ... b1 b 0
s n1 s n2 ... s1 s 0
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Gate Level Full Adder
Ai
0
0
0
0
1
1
1
1
3 - 16
Bi
0
0
1
1
0
0
1
1
Ci
0
1
0
1
0
1
0
1
Ci+1
0
0
0
1
0
1
1
1
Si
0
1
1
0
1
0
0
1
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Full Adder - Expressions
si  ai  bi  ci
ci 1  ai .bi  ci .( ai  bi )
where
 is exclusive OR
. is the AND operation
 is the OR operation
- verify that this corresponds to the gate-level implementation.
3 - 17
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Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside
A 4-bit Ripple-Carry Adder
3 - 18
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Carry Lookahead Addition
 We
can pre-compute the carry
 The carry in bit 4 (C4) is 1 if any two of A3, B3 or C3 are 1.
C4  A3 B3  C3 A3  C3 B3
 A3.B3  C3(A3  B3 )
 G3  P3C3
 P3 is called the propagate bit, and G3 the generate bit
C4  G3  P3C3  G3  P3(G2  P2C2 )  G3  P3(G2  P2(G1  P1C1 ))
   G3  P3G2  P3 P2G1  P3 P2 P1G1  P3 P2 P1C0
 So every carry bit can be pre-computed using all the previous
inputs.
 Pre-computation can be done in 2 gate delays.
3 - 19
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Storage Elements: R-S Latch
The
R-S Latch
0
1
1
0
•The output (a) of the R-S latch can
be set to 1 by momentarily setting S
to 0 while keeping R at 1.
•If S is set to 1 the output stays at
0.
1
0
1
•Conversely, the output can be set
to 0 by keeping S at 1 and
momentarily setting R to 0.
•When R is set back to 1, the output
stays at 0.
The flip-flop (R-S latch) is a bi-stable element
3 - 20
0
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Storage Elements: Gated D Latch
The R-S Latch
•The gated D larch is an extension of the R-S latch
•Two inputs: data (D) and write enable (WE)
•When the WE (write enable) is set to 1, the output of the latch
is set to the value of D.
•The output is held until WE is “asserted” (set to 1) again.
3 - 21
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Registers
A 4-bit register made of four D latches
3 - 22
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Memory - 1
A large number of addressable fixed size locations
 Address
Space
n bits allow the addressing of 2n memory locations.
 Example: 24 bits can address 224 = 16,777,216 locations
(i.e. 16M locations).
 If each location holds 1 byte then the memory is 16MB.
 If each location holds one word (32 bits = 4 bytes) then it is 64 MB.
3 - 23
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Memory - 2
 Addressability
 Computers are either byte or word addressable - i.e. each memory location
holds either 8 bits (1 byte), or a full standard word for that computer
(typically 32 bits, though now many machines use 64 bit words).
 Normally, a whole word is written and read at a time:
 If the computer is word addressable, this is simply a single address location.
 If the computer is byte addressable, and uses a multi-byte word, then the word
address is conventionally either that of its most significant byte (big endian
machines) or of its least significant byte (little endian machines).
3 - 24
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Building a Memory
A[1:0]
 Each
bit
 is a gated D-latch
 Each
location
 consists of w bits (here w = 1)
 w = 8 if the memory is byte
addressable
 Addressing
 n locations means log2n
address bits (here 2 bits => 4
locations)
 decoder circuit translates
address into 1 of n addresses
3 - 25
WE
D
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Memory Example
A 22 by 3 bits memory:
•two address lines: A[1:0]
•three data lines: D[2:0]
•one control line: WE
One gated
D-latch
3 - 26
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Using Memory Building Blocks
 Building an 8K byte memory using chips that are 2K by 4 bits.
 CS = chip select:
A10-A0
A12-A11
3 - 27
d
e
c
o
d
er
2K x 4 bits
2K x 4 bits
CS
CS
2K x 4 bits
2K x 4 bits
CS
CS
2K x 4 bits
2K x 4 bits
CS
CS
2K x 4 bits
2K x 4 bits
CS
CS
when set, it enables
the addressing,
reading and writing
of that chip.
This is an 8KB
byte addressable
memory
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Memory One Word Wide
 Use the previous memory block of 8K x 1 byte to build a memory that is 64K
words, with each location one word of 32 bits.

what are the address lines if the memory is word addressed? or byte addressed?
A? - A?
A? - A?
3 - 28
d
e
c
o
d
er
8K x 1B
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Finite-State Machines
input
Combinational
Logic Circuit
output
Storage
Element




3 - 29
Output is a function of the input and the state
The function is computed by the combinatorial logic circuit
The state is stored in the storage element
The state is also a function of itself and the input
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FSM Example
1
0
01
grp 1 on
all off
00
DETOUR
0
1
10
0
0,1
 Three groups of lights to be lit in a
sequence: group 1 on, groups 1 &
2 on, all groups on, all off.
 The lights are on only if the main
switch is on.
 Four states: so we need two bits
to identify each state.
all on
11
grp 1,2 on
1
d[1:0]
S
switch
2
2
Two bit
Storage
3 - 30
out1
out2
out3
Combinational
Logic Circuit
clock
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FSM Example
When
is group 1 on?
 in states 01, 10 and 11 - but only when the switch is on!
out1  (S0.S1  S0.S1  S0.S1).switch
out2  (S0.S1  S0.S1).switch
out3  (S0.S1).switch
When
do we switch to the next state?
 at every clock cycle the two bits are updated
 d[1:0] is the state at the next clock cycle; it is a function of the
input (switch) and the current state.
 can you come up with a logic expression for d0 and d1?
3 - 31
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The LC-2
as a
Finite
State
Machine
3 - 32
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Data Path of
the LC-2
3 - 33