MOS Field-Effect
Transistors (MOSFETs)
1
Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to
100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
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Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at
the top of the substrate beneath the gate.
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Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is
determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS.
Note that the depletion region is not shown (for simplicity).
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Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS,
is kept small. The device operates as a linear resistor whose value is controlled by vGS.
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Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered
shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
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Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated
with vGS > Vt.
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Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is
pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape.
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Figure 4.8 Derivation of the iD–vDS characteristic of the NMOS transistor.
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Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is
formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the
body terminal for the p-channel device.
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Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an
arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c)
Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device
operation is unimportant.
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Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of
current flow indicated. (b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.
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Figure 4.12 The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’n W/L = 1.0
mA/V2).
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Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.
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Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode
region and in the saturation region.
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Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus
reducing the effective channel length (by DL).
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Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology
and, for a given process, is proportional to the channel length L.
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Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output
resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22).
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Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source
lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and
the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.
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Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region
and in the saturation region.
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Figure E4.8
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Table 4.1
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Figure 4.20 Circuit for Example 4.2.
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Figure 4.21 Circuit for Example 4.3.
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Figure E4.12
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Figure 4.22 Circuit for Example 4.4.
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Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown.
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Figure 4.24 Circuit for Example 4.6.
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Figure 4.25 Circuits for Example 4.7.
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Figure E4.16
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Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of
the amplifier in (a).
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Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q.
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Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal
swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not allow for
sufficient negative signal swing.
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Figure 4.28 Example 4.8.
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Figure 4.28 (Continued)
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Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2
represent extremes among units of the same type.
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Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b)
reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate
using a capacitor CC1; (e) practical implementation using two supplies.
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Figure 4.31 Circuit for Example 4.9.
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Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
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Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I
using a current mirror.
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Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.
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Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier.
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Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34.
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Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length
modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.
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Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model.
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Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can
be added between D and S in the T model of (d).
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Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative
representation of the T model.
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Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body.
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Table 4.2
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Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations.
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Figure E4.30
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Table 4.3
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Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for
small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model
implicitly utilized.
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Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent circuit with
ro neglected.
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Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the
amplifier in (a). (c) The common-gate amplifier fed with a current-signal input.
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Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c) Small-signal
analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower.
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Table 4.4
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Table 4.4 (Continued)
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Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which
the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb neglected (to simplify
analysis).
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Figure 4.48 Determining the short-circuit current gain Io /Ii.
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Table 4.5
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Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier
in (a) delineating the three frequency bands of interest.
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Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a)
simplified at the input and the output;
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Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq;
(d) the frequency response plot, which is that of a low-pass single-time-constant circuit.
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Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected.
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Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are
sufficiently separated for their effects to appear distinct.
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Figure 4.53 The CMOS inverter.
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Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b)
graphical construction to determine the operating point; (c) equivalent circuit.
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Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical
construction to determine the operating point; (c) equivalent circuit.
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Figure 4.56 The voltage transfer characteristic of the CMOS inverter.
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Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms;
(c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the
capacitor discharge.
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Figure 4.58 The current in the CMOS inverter versus the input voltage.
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Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the
case the substrate (B) is connected to the source (S).
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Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = –4 V and kn(W/L)
= 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iD–vDS characteristics; (c) the iD–vGS
characteristic in saturation.
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Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the
saturation regions. The case shown is for operation in the enhancement mode (vGS is positive).
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Figure 4.62 Sketches of the iD–vGS characteristics for MOSFETs of enhancement and depletion types, of both polarities
(operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that for generality
somewhat different values of |Vt| are shown for n-channel and p-channel devices.
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Figure E4.51
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Figure E4.52
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Figure 4.63 Capture schematic of the CS amplifier in Example 4.14.
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Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 mF and CS = 0 (i.e., CS removed).
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Figure P4.18
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Figure P4.33
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Figure P4.36
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Figure P4.37
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Figure P4.38
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Figure P4.41
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Figure P4.42
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Figure P4.43
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Figure P4.44
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Figure P4.45
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Figure P4.46
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Figure P4.47
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Figure P4.48
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Figure P4.54
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Figure P4.61
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Figure P4.66
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Figure P4.74
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Figure P4.75
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Figure P4.77
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Figure P4.86
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Figure P4.87
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Figure P4.88
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Figure P4.97
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Figure P4.99
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Figure P4.101
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Figure P4.104
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Figure P4.117
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Figure P4.120
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Figure P4.121
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Figure P4.123
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