RMM3 Discussion
Chapter 1
Introduction
Description:
 System-On-Chip design ←→ board design
 Reuse concept: team size、schedule and quality
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Silicon and tool technologies move so quickly
1.1 Goals: For two audiences, integrators and macro designers.
Common set of problems
 Time-to-market pressure
 Quality: performance、area and power
 Chip complexity ←→ verification difficult
 Design flow、tools and guideline change
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Topic
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Software component
Reusable macros fit into a SoC
Design reusable soft macros
Soft macros → Reusable hard macros
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Integrate soft and hard macros
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Verify the timing and functionality
Definitions
 Macro、Core、Block and IP
 Subblock、Soft macro and Hard macro
Virtual Socket Interface Alliance(VISA)
 An industry group
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design reuse: tool interfaces and documentation
Virtual component and Firm macro
1.2 Challenge:
Effective block-based design methodology
 Easy to integrate
 Robust, no functional verification of the internal macros
Reusable vs. Usable: robust and correct
 Good documentation、code、through commenting、well-designed verification
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and robust scripts
Design phase → integration phase
Speed the design、verification and debug
Requirements for the reuse
 Solve a general problem
 Multiple technologies
 Variety of simulators
 Standards-based interfaces
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Verified independently
Running real software
Fully documented the valid configuration and parament
1.3 Business Model: Causal reuse provides about a 2-3x benefit.
Example:
 1 designer-days: 100 gates,
 1000 designer-days(5 person/ 1 year): 100k gates
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10,000 designer-days(500 person/ 1 year): 10M gate
Dedicated group to developing reusable blocks.
Reusable blocks is very expensive: more than a 3x effort
 Buy-before-build
It is likely that the convergence of chip architectures using reuse-based design will
also enable new markets in software-differentiated products and very specialized,
high-value hardware.
Chapter 4
The Macro Design Process
4.1 Overview : A library reusable components
 Configurable→ Harder to verify
 Different multipliers、caches and cache controllers
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 Different bus widths
Standard interfaces: VCI、AMBA..etc
Defensive design practices(chapter5):
 timing closure、functional correctness and packaging
 keep the design as simple as possible
Complete set
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Synthesizable RTL
Verification IP(VIPvs.IIP): BFM、monitor and test suites transaction–
based , chapter 7)
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 Initial verification
 Rapid configurable test bench
 Easy to integrate to the chip-level test bench
Synthesis scripts
Documentation
Design Process
Figure 4-3 Phase of IP design
It is often said that the earlier a mistake is made in the design process, the more costly
it is.
4.2 Features:
 Initial specification
 define the configuration parameters for the IP
4.3 Planning and Specification
Key Document
 Functional specification
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Pin definitions
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Parameter definitions: specific configuration
Register definitions: software-programmable registers
Additional information to explain: interaction description or block
diagrams
 Performance and physical implementation
 Clock frequencies and number of clock domains
 Number of resets and their timing relationships
 Power vs. performance
Verification specification
 Define the test environment to verify the IP
 Directed test、random testing
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Packaging specification
 installation、configuration and synthesis scripts
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Development plan: non-technical contents
 deliverables、schedule…etc.
High-level model: transaction-level models vs. functional model
4.4 Macro Design and Verification
Macro design process
 Technical specification
 Macrocell and sub-block
 RTL
 Functional verification
 Implementation verification
 Develop synthesis scripts
 Run synthesis
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Perform scan insertion
Perform power analysis
Figure 4-4 Sub-block development process
Figure 4-5 Sub-block integration process
4.5 Soft Macro Productization
Figure 4-7 Productizing soft macros
Soft macro activities
 Develop a prototype chip
 First time 90%, but In the system 50%
 Functionally correct
 Complies with the standards
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 Compatible with the kind of HW/SW environment
Verilog and VHDL
Test on several simulators
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Synthesize on multiple technologies
Perform gate-level simulation
Formal verification
Creat/update user documentation
Alpha testing and release