Reliability and Wireability Optimizations for Chip Placement
on Multichip Modules
Jing Lee
Department of Electronic Engineering
Southern Taiwan University of Technology
Tainan, Taiwan 710, R.O.C.
Email: leejing@mail.stut.edu.tw
Abstract
Index Terms— Force-directed algorithm, MCM, Placement, Thermal force.
The chip placement problem of MCM designs is to map the chips properly to the chip sites
on the MCM substrate. Chip placement, affects not only the thermal characteristics of an MCM
but also routing efficiency, which translates directly into manufacturability, performance, and cost.
This paper presents a solution methodology for the optimal placement problem considering both
thermal and routing design objectives simultaneously. The coupling is achieved through use of a
hybrid-force model that is a combination of the traditional interconnection-force model and a
novel thermal-force model. The placement procedure can be used as a design tool to place chips
and then determine the tradeoffs which can be made in placing for reliability and wireability.
Experiments on five examples including three benchmarks show that the present algorithm yields
very high quality results.
Nomenclature
Cij = cost of assigning chip ci to chip site sj
Cr = control parameter in the interconnection-force model
c = chip
Fx = force in x direction
TEMP-2003-55.R1
1
Fy = force in y direction
fij = thermal-force exerted on ci caused by cj
h = heat transfer coefficient, W/m2K
kij = edge weight between ci and cj
L = total routing length
l = number of chip sites
m = number of movable chips
n = number of chips
p = pitch of chip sites, mm
q = power, W
r = coefficient of the repulsion force
Sf = scaling factor
s = chip site
T = temperature, K or oC
x, y = Cartesian coordinates, mm
Greek
 = change in variable
 = pitch ratio, py / px
 = failure rate, Fit
 = weighting factor
Subscripts
i, j = index
TEMP-2003-55.R1
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M = center of mass
s = system
x, y = x-, y- direction
Superscripts
C = interconnection-force
T = thermal-force
(r, c) = r-c-substrare
I. INTRODUCTION
Multichip packaging technology has received widespread attention in the electronics
industry. The use of multichip modules (MCM) promises to increase circuit density and enhance
circuit performance beyond that otherwise will be possible through the use of VLSI and surface
mount technology. However, this trend results in higher heat flux densities at the substrate. The
heat generated by the chips must be removed efficiently because virtually all failure mechanisms
are accelerated as temperature rises.
Chip placement, which is concerned with mapping the chips to the chip sites on the MCM
substrate, is a key aspect in physical design cycle. A poor placement takes up larger areas,
degrades performance, and often leads to a difficult or even impossible routing task. Also, since
placement directly determines the minimum length of the interconnection wiring for the circuit,
and wiring delay usually dominates the response time of the electrical signals carried by the
wiring, it is fair to say that placement is crucial to the performance of the resulting circuit.
Therefore, the optimal chip placement on MCM requires the satisfaction of multiple, possibly
conflicting, design objectives. In particular, the minimization of system failure rate and the total
TEMP-2003-55.R1
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routing length are design objectives of prominent interest.
Historically, placement techniques have been developed primarily on the basis of wireability.
Sherwani [1] provides a summary of the classic techniques. These algorithms typically
concentrate on minimizing total routing length, while others focus on minimizing wire crossovers
and vias [2]. However, with the increased demand for high quality and long-term reliable
performance, techniques are developed to address placement for reliability. Some studies have
focused on reliability improvement for power hybrid circuits (PHC) [3], for convectively cooled
PCB [4]-[9], for VLSI [10], [11], and for MCM [12]-[16].
Recently, placement for reliability and wireability has also received attention [17]-[21].
Most of them are presented for convectively cooled PCB, and the others are presented for MCM
design. In particular, Osterman and Pecht [17] presented a force-directed technique for the
multiobjective optimal placement. In their approach, they first constructed a position-adjacency
matrix mapped from the optimal placement based on reliability. Subsequently, they combined the
position-adjacency matrix with the connectivity matrix, constructed from the signal nets by a
weighting factor, to form a hybrid matrix. After that, the force-directed placement technique was
used to obtain the relative positions of the modules based on the hybrid matrix. Their method
gives tradeoffs of objectives but not Pareto optimal solutions. For the same problem, Lee et al [18]
presented an ordered best-first search algorithm to obtain Pareto optimal solutions. In their
algorithm, a thermal wake function is used to predict the temperature profile of the components
on a PCB. Since their algorithm is based on the branch-and-bound technique, it is very time
consuming for huge problems. Queipo and Gil [19] presented another placement procedure for
the multiobjective problem. They use a heat transfer solver, which is based on thermal network
approach, to predict the temperatures of the heat sources. A genetic algorithm is then presented to
search near Pareto optimal solutions. In addition, placement for reliability and wireability on
TEMP-2003-55.R1
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PHC designs was studied by Lee and Chou [20]. Their method begins with a quadrisection
partitioning procedure to place the components that generate obvious heat, followed by a
force-directed algorithm to place the components that generate negligible heat. More recently,
Huang et al. [21] presented a fuzzy force model to manage the multiobjective problem on an
edge-cooled package.
This paper deals with the coupling reliability and wireability optimizations problem for
MCM designs. The coupling is achieved through use of a hybrid-force model that is a
combination of the traditional interconnection-force model and a novel thermal-force model. The
rest of this paper is organized as follows: Problem is described in Section II. Force models are
introduced in Section III. Placement algorithms are presented in Section IV. Examples with
computational results are given in Section V. Conclusions are drawn in Section VI.
II. PROBLEM DESCRIPTION
Consider a two-dimensional substrate on which chips are to be placed. The substrate is
characterized in terms of a finite array of chip sites. The pitch (i.e. center-to-center spacing) of
the chip sites in x-direction, px, can be different from the pitch in y-direction, py. A matrix
location or chip site is represented by a point in an x-y coordinate system. Chips are the entities
to be assigned to chip sites on the substrate. Some chips’ locations have been predetermined for
timing or cooling considerations. These chips are called fixed chips; the others are called
movable chips. In general, I/O pads are grouped into high density connectors and are located
around the border of the substrate. Each connector is considered as a fixed chip with zero power
in the study. A typical example of MCM is depicted in figure 1, where the edges of same
terminals are depicted as only one edge. This example includes 37 chips, 18 high density
connectors, and 7118 signal nets. More data listed in Table 1 about this example will be described
TEMP-2003-55.R1
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in Section V further.
Fig. 1
Chip placement and rat’s nest of MCC2.
A. Routing Length Estimation
Chips contain pins for interconnection by physical wires to form signal sets. In this work,
the pins on chips are ignored and the distance is measured from the center of the chip. Hence, a
signal set becomes a subset of chips, and a signal set specification defines the interconnection of
all chips on a specific substrate. The routing length of a signal set is defined as half-perimeter of
the smallest rectangle, which encloses the chips in the signal set. The half-perimeter method is
commonly used in literatures [22]. The total routing length estimation is then obtained by
summing the individual estimates.
B. Failure Rate Estimation
The failure rate of a chip is estimated using the Arrhenius relation as:
E  1
1 
λ(Ti )  λ(Tr )  exp  a   
 B  Tr Ti 
(1)
where (Ti) and (Tr) are the failure rates of the chip at a temperature of Ti K and at a reference
temperature of Tr K, respectively; Ea is the activation energy (eV); B is the Boltzmann's constant.
TEMP-2003-55.R1
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To determine the failure rate of an individual chip, various operating parameters need to be
specified. Without loss of generality, in this study, all chips are assumed to be the same factors of
(Tr) and Ea, which are 1 Fit (i.e. 10-9/hour) and 1 eV, respectively. The system failure rate of an
MCM is given by the sum of the individual chip failure rates.
C. Problem Definition
The placement problem dealt with in the study can be stated as follows: given a set of n
chips {ci 1  i  n} including a subset of m movable chips {ci 1  i  m}, a set of chip powers {qi
1  i  n}, a set of l chip sites {sj 1  j  l} on a two-dimensional substrate, and a netlist
interconnecting chips, assign each movable chip to one of the chip sites such that the total routing
length L and the system failure rate s can be minimized. Note that even one of the objectives
optimization problem is considered as a NP-hard combinatorial problem [1], which requires
exponential order of computation time. The two-objective optimization problem is a much harder
combinatorial problem. Generally, no solution satisfied the two objectives simultaneously. Only
Pareto optimal solutions can be obtained. The Pareto optimal solution of a two-objective
optimization problem is the one for which any further improvement of either objective function
will cause the degrading of the other.
III. FORCE MODELS
Force-directed technique is accomplished numerically by developing interactive forces
between chips. These forces are created by the designer through defining connections between
chips. In terms of wireability, a popular force model, namely interconnection-force model, is that
each chip exerts forces of attraction on chips connected by signal nets, and repulsion forces are
used to keep chips apart for those that are not connected [24]-[28]. More recently, force models
TEMP-2003-55.R1
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for reliability, namely thermal-force models, are also presented [14], [16]. Basically, these
thermal-force models give repulsion forces between any two chips according to their heat
dissipations. In the section, a hybrid-force model is presented by coupling the two different types
of force models.
A. Thermal-Force Model
The thermal-force model in [16] is based on the assumption that heat loss from the sidewalls
of the substrate is insignificant compared to the top and bottom sides of the substrate. Therefore,
a rectangular substrate of several heat sources can be similarly transformed into an unbounded
substrate containing an infinite number of mirror image heat sources as shown in figure 2. The
mirror image substrate at the rth row and the cth column is called the r-c-substrate. The new
configuration generated by this transformation has the property that it leaves unchanged the
temperature distribution within the original region [29], [30].
Y
Mirror image
heat sources
2-2-substrate
Row
2
qi
qj
qj q
i
qi
qj
qj q
i
qi
1
qi q
j
qj qi
qi q
j
qj qi
qi q
j
0
qi
qj q
i
qi
qj q
i
qi
-1
qi q
j
qj qi
qi q
j
qj qi
qi q
j
-2
qi
qj q
i
qi
qj q
i
qi
Column
-2
qj
qj
-1
0
qj
qj
1
qj
qj
X
qj
2
Real substrate
Fig. 2
Replace insulated boundaries by mirror image sources [16]
In the unbounded substrate, heat flows everywhere from every heat source, and the heat flux
is reciprocal of the square of the distance from the heat source in the steady state condition. To
TEMP-2003-55.R1
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optimize the system reliability of an MCM, it is needed to distribute heat sources (i.e. chips) on
the substrate as evenly as possible to avoid hot spots, and to maintain a uniform thermal profile.
The phenomena of heat transfer from other chips to a specific chip can be viewed as other chips
pushing the specific chip with forces, named thermal-force. The thermal-force exerts on ci in the
real substrate by cj in the r-c-substrate is formulated as
f ij( r,c )
0,
if ci is fixed or c (jr ,c )  ci

qj


,
otherwise
 ( x ( r,c ) ) 2  ( y ( r,c ) ) 2
ij
ij

(2)
)
)
where xij( r,c )  x (jr,c )  xi , yij( r,c )  y (jr,c )  yi , and ( x (r,c
, y (r,c
) denotes the location of the
j
j
image chips of cj in the r-c-substrate. The location of cj in the real substrate (i.e. 0-0-substrate) is
simply denoted as (xj, yj).
In practical MCM designs, the chip pitch in x-direction may not be equal to the one in
y-direction. This implies that the same magnitude of thermal-forces exerted on a chip in different
directions might have different moving effects. In order to cover the cases of unequal pitches, our
strategy is to transform the unequal-pitch substrate to an equal-pitch substrate by simply
multiplying the distances in x-direction by a factor of  = py / px. Therefore, the thermal-force
model is modified as
f ij( r,c )
0,
if ci is fixed or c (jr ,c )  ci

qj


,
otherwise
(
r,c
)
2
 (x )  ( y ( r,c ) ) 2
ij
ij

(3)
f ij(r,c ) can be broken down into the components of
fxij( r,c )  f ij( r,c )  cosij( r,c )
and
TEMP-2003-55.R1
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in x-direction
(4a)
fyij( r,c )  f ij( r,c )  sin ij( r,c )
in y-direction
(4b)
where
 yij( r,c ) 

( r,c ) 


x
ij


 ij( r,c )  tan -1 
(5)
Expanding the formulation to cover all n chips in the unbounded substrate, the thermal-force
exerts on ci can be formulated as

a
a 1
T
Fxi    fxij( 0 ,0)      fxij(  a,c )  fxij( a,c )    fxij( r,a )  fxij( r,a )  
 
a 1
r   a 1
c   a
j 1 
n
in x-direction
(6a)
and

a
a 1
T
Fyi    fyij( 0 ,0)      fyij(  a,c )  fyij( a,c )    fyij( r,a )  fyij( r,a )   in y-direction
 
a 1
r   a 1
c  a
j 1 
n
(6b)
In theory, the maximum value of a in formula (6a) and (6b) must be infinity. However, it was
proven that the maximum value of a of five is adequate [16].
B. Interconnection-Force Model
In this model, the interconnection among chips is represented by a network. Each signal net
with t pins is simulated by a clique with an edge weight of 4/(t2-mod(t,2)) to modify the edge
exaggeration [31]. If two chips are connected by more than one edge, these edges are reduced to
one edge with the sum of the individual edge weight. If ci and cj are linked by an edge with
weight kij in the network, there is an attractive force proportional to the weight times the distance
between them. On the other hand, there are repulsion forces between unconnected chips.
Recall that the system includes n chips and {ci 1  i  m} is the set of movable chips. The
coefficient of the repulsion force between ci and cj is defined by
TEMP-2003-55.R1
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0, for either i  j or kij  0
rij  
for kij  0
 R,
(7)
where U is the number of unconnected pair, Cr is a controlling parameter, and R is defined by the
equation
R
m m
1
kij

U  C r i 1 j 1
(8)
The force exerted on a movable chip ci by all other chips is
n 
ηΔxij
FxiC    -k ij  ηΔxij  rij 

ηΔxij  Δyij
j 1





in x-direction
(9a)
n 
Δyij
FyiC    -k ij  Δyij  rij 
j=1
ηΔxij  Δyij





in y-direction
(9b)
and
In addition, it is also desirable to have the center of all chips be in the geometric center of
the layout plane so that the placement of chips is balanced. Physically, it is equivalent to have the
forces acted upon the set of all chips being removed. The force on the center of mass, denoted by
FxMC and FyMC , are calculated by the following equations:
m
C
FxM
  FxiC
i 1
(10a)
and
m
C
FyM
  FyiC
i 1
(10b)
Once FxMC and FyMC are calculated, the force equation are subtracted by the portion of
the center of mass forces. Then, the force equations become
TEMP-2003-55.R1
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n 
ηΔxij
FxiC    -k ij  ηΔxij  rij 
j=1
ηΔxij  Δyij

 Fx C
 M

m

in x-direction
(11a)
 Fy C
 M

m

in y-direction
(11b)
and
n 
Δyij
FyiC    -k ij  Δyij  rij 
j=1
ηΔxij  Δyij

C. Hybrid-Force Model
For coupling the reliability and the wireability objectives, a hybrid-force model is obtained
by combining the thermal-force and the interconnection-force models as
Fxi  ω  FxiT  (1  ω)  S f  FxiC
(12a)
Fyi  ω  FyiT  (1  ω)  S f  FyiC
(12b)
and
where 0    1 is the weighting factor representing the relative importance of the optimization
criteria; Sf is a scaling factor to render the average contribution of the interconnection-force in the
sum comparable in magnitude to the average contribution of the thermal-force. The thermal-force
and the interconnection-force on ci caused by cj are basically proportional to

qj
(xij )  ( y ij ) 2
2

and k ij xij  yij , respectively. It is reasonable to define Sf as
Sf 
where qav 
qav
2
( ηp x ) 2  p y

k av  ηp x  p y 
1 m
1 m n
qi and k av   kij .

m i 1
m i 1 j 1
TEMP-2003-55.R1

12

qav
3
4k av p y
(13)
IV. PLACEMENT PROCEDURE
The placement procedure presented here consists of two phases. In phase one, the relative
positions of movable chips are determined by setting the nonlinear system of equations given by
(12) to zero and solving the system of equations. In phase two, movable chips are placed into
chip sites to ensure minimum displacement from the placement obtained by Phase one.
A. Zero-Force Placement
In phase one, a Modified Newton-Raphson (MNR) method [16] is used to solve the system
of equations given by (12) to find the zero-force position of every chip. The MNR method begins
with a randomly generated placement. Then, movable chips are moved to new positions by the
following equations:
xi ( new )  xi  0.5 
Fxi
Fxi'
(14a)
and
yi ( new )  y i  0.5 
Fyi
Fyi'
(14b)
where Fxi' and Fyi' are the partial derivations of Fxi and Fyi to xi and yi, respectively. At
the new position, Fxi , Fxi' , Fyi and Fyi' are recomputed, and equations given by (14) are
again used to update chip positions. Thus starting with an initial placement, a sequence of
placement is generated. The final result of this sequence, namely zero-force placement, is the
placement that all chips move to their zero-force target locations.
In the phase, the hybrid force model allows the layout designer to place chips for either
reliability or wireability depending on the setting values of .
TEMP-2003-55.R1
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B. Chip Assignment
Zero-force placements usually are physically unacceptable from either the standpoint that
the chips overlap, or that the technology requires placing the chips in arrays. A chip assignment
method, therefore, is proposed to assign movable chips to chip sites for as little displacement as
possible.
The assignment problem can be put in the form as follows: Consider the situation of m chips
to be assigned into l chip sites. Let aij be a Boolean variable describing the assignment of chip ci
to chip site sj
 1, if assign ci to s j
aij  
if not
 0,
(15)
It is required that one chip can occupy one and only one chip site, and on each chip site no more
than one chip is allowed. Therefore
m
a
ij
1
for j = 1, 2, …, l
(16a)
for i = 1, 2, …, m
(16b)
i 1
l
a
j 1
ij
1
The objective is to
m
minimize
l
 C a
i 1 j 1
ij ij
(17)
where Cij represents the cost of assigning chip ci to chip site sj. Three cost functions, rectilinear
distance from the chip to chip site, the Euclidian distance, and the square of the Euclidian
distance, are usually considered. The Euclidian distance is chosen as the cost function in this
study since Quinn and Breuer pointed out that the square of the Euclidian distance is the best one
for circuit placement problems [25]. The linear assignment problem has been extensively studied
TEMP-2003-55.R1
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in literatures [32]. Here, it is solved by the Hungarian method [33].
V. EXAMPLES AND COMPUTATIONAL RESULTS
Five MCM examples are proposed to examine the present method and provide some insight
into the method. To simplify the analysis, all examples are treated as having the same package
structures and cooling conditions as shown in figure 3. This package consists of a sandwich
structure formed from the ceramic multiplayer substrate-epoxy adhesive-aluminum heat sink with
thicknesses of 9, 0.076, 1.27 mm, respectively. Within each layer, the material is assumed linear,
isotropic, and homogeneous. Temperature and heat flow are continuous at interfaces between
layers. Thermal conductivities of the substrate, the epoxy layer, and the heat sink are 39.4 W/mK,
0.276 W/mK, and 195 W/mK, respectively. The known heat sources are treated as heat fluxes
directly from the substrate. Heat loss from the package into the board and from the finned side is
quantified by heat transfer coefficients, htop and hbot. Because the average heat flux is very high in
the examples tested, conditions are selected for force convection at a velocity of 2.5 m/s for the
board, and jet impingement at a velocity of 0.5 m/s for the finned sides. Correspondingly, the
average heat transfer coefficients for htop and hbot are 43.8 W/m2 K and 832 W/m2 K, respectively.
Y
h top
0
Epoxy
Heat sink
Multilayer
substrate
Fig. 3
TEMP-2003-55.R1
X
hbot
Package structure for an MCM
15
A TAMS (Thermal Analyzer for Multilayer Structures) program developed by Ellison [34] is
used to predict chip temperatures on a substrate. This computer program can predict the
steady-state temperature in four-layer-rectangular structures with anisotropic conductivity,
lumped thermal resistances, and planar-discrete sources.
In the present method, Cr in formula (8) is the only parameter that is needed to specify its
best value. Unfortunately, no systematic way of setting Cr has been found until now. In this work,
the best value of Cr is determined by a trial and error method under the condition of  =0. Then,
the obtained value of Cr is applied to the cases of different values of  .
A. Information of Test Cases
Two designed MCMs, M12 and M16, and three benchmarks, MCC1, MCC2, and GEMI, are
examined by the present method and provide some insight into the method. Some MCM
information is shown in Table 1. For M12 and M16, the dimensions of chips are 5.1 mm square
and the substrates are 30.5 mm square. Each chip dissipates one watt. In addition, M16 includes 4
connectors fixed at the middle points of the four edges of the substrate. The interconnections
among chips for M16 can be found in Fig. 6(b).
Table I
Module Chip
Chip
site
MCM information
Net Connector
Edge length
(mm)
Power dissipation
(power × chip number)
M12
12
4×3
0
0
30.5
1 W×12
M16
16
4×4
37
4
30.5
1 W×16
MCC1
6
3×2
802
4
45
25 W×2, 16 W×4
MCC2
37
7×7
7118
18
152.4
GEMI
29
5×6
4969
18
127.5
30 W×15, 27 W×3, 25 W×5,
16 W×9, 13 W×3, 7 W×2
30W×7, 27W×3, 25W×5,
TEMP-2003-55.R1
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16W×9, 13W×3, 7W×2
MCC1 and MCC2 are two standard benchmarks that are commonly used to compare both
placement and routing algorithms [35]. MCC1 consists of 6 chips, 802 nets, 2496 pins, and 765
I/O pads on a 45 mm square substrate. Here, the 765 I/O pads are grouped into four high density
connectors located at the middle points of the four sides of the substrate. There are two types of
chips: C448, with 550 mils edge length; and C272, with 330 mils edge length. The MCM consists
of four C448s and two C272s.
MCC2 contains 37 chips, 548 I/O pads, and 7118 signal nets. The I/O pads are grouped into
18 high density connectors. The sizes of the substrate and the active substrate are square
measuring 152.4 mm and 137.725 mm, respectively. The active substrate is divided into a 7-by-7
matrix of identical chip sites. Each chip and chip site are square with a 16.764 mm and a 19.675
mm edge, respectively. Chip placement and rat’s nest of MCC2 have been shown in figure 1.
Another example, GEMI, is derived from the IBM’s GEMI 30-chip-site module [36]. The
substrate of GEMI, which is square measuring 127.5 mm on the side, is divided into a 5-by-6
matrix of identical chip sites. Each chip site is a rectangle of 18.45 mm × 22.05 mm in size.
Twenty-nine chips, with the chip sizes ranging from 12.9 to 17.4 mm on the side and power
ranging from 7 W to 30 W, are placed on the substrate.
Since there lacks of the chip power data of MCC1 and MCC2, the data of chip power in
MCC1 and MCC2 are produced from the data of GEMI. Also, since the net list of GEMI is
unknown, the net list in GEMI is obtained by geometrically partitioning the pin placement of
MCC2. So, 18 high density connectors as those in MCC2 are added into GEMI.
B. Effect of 
M12 is designed for demonstrating the effect of introducing  into the thermal-force model.
Figures 4(a) show the zero-force placement of M12 obtained by setting  = 1. Obviously, this
TEMP-2003-55.R1
17
placement is very close to the best placement for full custom design. However, if the final
placement is to place the chips in four rows by three columns and such a placement is of the pitch
ratio 3/4, it needs a chip assignment procedure to transform the zero-force placement into the
array-type placement. Since the difficulty of the chip assignment problem and the error caused by
the assignment algorithm strongly depend on how close of the zero-force placement to its final
placement, it is always necessary to let the zero-force placement as close to the final placement as
possible. By contrast, the placement in figure 4(b) is obtained by setting  = 3/4 for considering
the unequal-pitch condition. It is obviously that this placement is more close to the final
placement than the placement in figure 4(a). Thus, both the difficulty of the chip assignment
problem and the error caused by the assignment algorithm are reduced. Of course, thermal
distortion is induced in the zero-force placement by introducing  into the thermal-force model.
In comparison figure 4(a) with figure 4(b) in chip temperatures, one can find that the thermal
distortion is tiny.
117
118
118
119
118
119
118
118
118
118
118
118
119
118
119
118
118
118
118
118
118
118
118
117
(a)  = 1
Fig. 4
(b)  = 3/4
Zero-force placements with temperature (oC) distributions of M12
C. Results of M16
M16 is designed to provide some insight into the transitions of the zero-force placements for
TEMP-2003-55.R1
18
gradually decreasing  from 1 to 0. The zero-force placements obtained by setting different
values of  are depicted in figures 5(a) through 5(f). For the case of  = 1, the zero-force
placement has an important feature that chips are placed apart to abound with the substrate due to
the actions of thermal-forces. Notice that thermal-forces are repulsion forces among chips and
boundaries of the substrate. Obviously, this placement is an optimum solution in reliability.
However, the placement also is a bad solution in wireability due to lack the information of
interconnections in the force model. By contrast, for the case of  = 0, chips are placed in a good
topology which reflects the interconnections of chips as shown in figure 5(f). But, the chips tend
to cluster together due to the actions of the attraction forces among connected chips. As a result, it
increases the difficulty in the chip assignment phase because of relatively small resolution of
chips into chip sites. So, the final placement as shown in figure 6(a) is not an optimum solution in
wireability. Given a small fraction of thermal-force into the hybrid-force model can substantially
decrease the clustering problem. An example is shown in figure 5(e), which is the case of  = 0.1.
Here, the zero-force placement is not only preserve the interconnection topology, but also places
chips apart. Thus, the final placement as shown in figure 6(b) is the optimum solution in
wireability. So, even wireability is the only optimization objective for a placement problem, a
fraction of thermal-force is still needed in the hybrid-force model. In addition, figures 5(a)
through 5(f) show that the total routing length of the zero-force placement is decreased with the
side effect of losing the array structure while decreasing .
D. Results of Benchmarks
Note that the final placement attained depends on its initial placement. For giving a fair
estimation of the present method, for each case the program runs ten times and for each time it
begins with a random placement. The result of each case is the mean of noninferior solutions of
the ten trials.
TEMP-2003-55.R1
19
(a) =1, L=802mm
(b) =0.7, L=621mm
(d) =0.3, L=369mm
Fig. 5
(e) =0.1, L=328mm
(f) =0, L=274mm
Zero-force placements of M16. L is the total routing length.
(a) =0, L=371mm
Fig. 6
TEMP-2003-55.R1
(c) =0.5, L=467mm
(b) =0.1, L=341mm
Final placements of M16
20
The solutions obtained by the present method and all feasible solutions obtained by
enumeration method for MCC1 are depicted in figure 7, where L and S refer to the total
routing length and the system failure rate, respectively. Since there are only two different types of
chips MCC1, only six different values of S are in the solutions. This figure clearly supports
that the solutions have better reliability and worse wireability while increasing . It also shows
that the solutions obtained by the present method are close to Pareto optima.
5
1.85
x 10
=[0,0.4]
 s (Fit)
1.8
=0.5, 0.6
1.75
feasible solutions
present results
1.7
=0.7
1.65
=0.8, 0.9 =1
1.6
1.8
2
2.2
2.4
2.6
L (mm)
Fig. 7
2.8
3
3.2
4
x 10
Placement results of MCC1. Numerals in [ ] represents interval notation.
Since the solution spaces of MCC2 and GEMI are huge, it is impossible to find out all
feasible solutions. Therefore, the solutions obtained by the present method are compared to 1000
randomly generated solutions. Both figures 8 and 9 show that the solutions obtained by the
present method are much better than randomly generated solutions. As   0.3 and 0.6 with
respect to MCC2 and GEMI, the solutions are of better reliability and worse wireability while
increasing . However, in the cases of  < 0.3 and 0.6 with respect to MCC2 and GEMI, the
trends are irregular owing to the clustering effect caused by interconnection-forces. Once again,
TEMP-2003-55.R1
21
the best solutions for wireability are not at  = 0 in both cases. Another important feature is that
the solutions at  = 0.9 are significantly improved in wireability and only slightly inferior in
reliability to the solutions at  = 1. So, for generating a placement coupling reliability and
wireability, setting  = 0.9 maybe a better choice than setting  = 1.
5
1.6
x 10
=0.1
1000 random solutions
present results
1.4
 s (Fit)
=0.2
=0.3
=0
=0.4
1.2
1
=0.5
0.8
0.6
0.4
=0.6
=0.7
=0.8
=0.9
0.6
0.8
=1
1.2
1
1.4
L (mm)
Fig. 8
6
x 10
Placement results of MCC2
5
1.6
x 10
1000 random solutions
present results
1.5
1.4
 s (Fit)
1.3
1.2
1.1
1
=0
=0.6
=[0.1,0.5]
=0.8
0.9
0.8
=0.7
4
=0.9
=1
5
6
L (mm)
Fig. 9
7
8
5
x 10
Placement results of GEMI. Numerals in [ ] represents interval notation.
TEMP-2003-55.R1
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D. Comparison of Algorithms
There are basically two kinds of heuristics, constructive algorithms and iterative
improvement approaches, for possibly solving the problem studied here. In general, iterative
improvement approaches start with an initial placement and repeatedly modify it in search of a
cost reduction. By applying stochastically accepted rules, iterative improvement approaches have
the hill climbing capacity [37]. However, these stochastically accepted rules also make these
methods inefficient. Additionally, these methods have to determine chip temperatures with
system failure rate of each candidate placement generated in every iterative procedure for
updating current placements. However, it is a very time consuming procedure to calculate the
chip temperatures. So, iterative improvement approaches generally need very long execution time
for solving the present problems, and thus these methods are unfeasible for even middle-sized
problems. By contrast, the present method, which belongs to the group of constructive algorithms,
constructs a placement from scratch by a sequential, deterministic procedure. It is unnecessary to
calculate chip temperatures and system failure rate during the placement procedure. So, the
present method is very fast, and can be applied for solving large-size problems. However, it is no
guarantee to obtain Pareto optima by the present method.
VI. CONCLUSION
This paper proposes a methodology to generate the placements that are tradeoffs between
reliability and wireability. The tradeoff is achieved through use of a hybrid-force model that is a
combination of an interconnection-force model and a thermal-force model. The layout designer
can place chips for either reliability or wireability by managing the selected weighting factor .
Five examples including three benchmarks were examined the present method. The main
conclusions are:
TEMP-2003-55.R1
23
1.
When  is higher than a critical value, a placement obtained by setting higher value of  is
superior in reliability and inferior in wireability to the one obtained by setting lower value
of .
2.
For wireability-optimization placement problems, the hybrid-force model with a fraction of
thermal-force is superior to the interconnection-force model.
3.
The placement obtained by setting  = 1 is of very high quality in reliability, but it usually is
of low quality in wireability; the placement obtained by setting  = 0.9 is significantly
improved in wireability and only slightly inferior in reliability to the placement obtained by
setting  = 1.
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