Multiobjective Optimal Placement for MCM Designs
Jing Lee (P4-16)
Department of Electronic Engineering
Southern Taiwan University of Technology
Tainan, Taiwan 710, R.O.C.
Email: leejing@mail.stut.edu.tw
ABSTRACT
This paper proposes a coupled reliability and
wireability placement procedure for the MCM designs.
The placement procedure is broken into two phases,
Phase I being the “zero-force placement,” and Phase II
being the “chip assignment.” In Phase I, a system of
simultaneous equations, based on a combination of the
traditional interconnection force model and a novel
thermal force model, are solved to determine the
optimum relative locations of chips. In Phase II, chips
are assigned into chip sites in order to distort the chips
positions obtained by Phase I as little as possible. Two
benchmarks, MCC1 and MCC2, have been examined
by the present methodology.
Index Terms—Placement, reliability, wireability,
MCM.
1. INTRODUCTION
Today’s densely packed submicron devices,
on-chip circuitry has become so fast that a significant
portion of the total delay in a processing unit is due to
the time required for signals to travel from one chip to
another [1, 2]. In order to minimize this delay, chips
must be placed close together. Multichip module
(MCM) technology has been introduced to significantly
improve performance by eliminating packaging. An
MCM is a packaging technique that places several
semiconductor chips, interconnected in a high density
substrate, into a single package.
Chip placement is concerned with mapping the
chips to the chip sites on the MCM substrate. The
optimal chip placement on MCM requires satisfying
multiple, possibly conflicting, design objectives. As
pointed out by Moresco [3], these design objectives
may be very different in nature- geometrical,
performance,
thermal,
mechanical,
and
cost
(manufacturing and maintenance). Two major design
objectives are related to the reliability (thermal/
mechanical/cost) and the wireability (performance/cost)
requirements of the chip placement design.
This paper examines coupling reliability- and
wireability-based chip placement for MCM. In most
cases no solution satisfies both conditions
simultaneously. Generally, only Pareto optimal
solutions exist. The Pareto optimal solution of a
two-objective optimization problem is the one for
which any further improvement of either one objective
function will cause the degrading of the other one.
The remainder of this paper is organized as
follows. Section 2 defines the multiobjective optimal
placement problem. Section 3 presents an overall view
of the force models. In Section 4, we describe the
placement procedure with algorithms. Section 5 gives
some experimental results, and Section 6 concludes this
paper.
2. PROBLEM DESCRIPTION
Consider a two-dimensional substrate on which
chips are to be placed. The substrate is characterized in
terms of a finite array of chip sites. A matrix location or
chip site is represented by a point in an x-y coordinate
system. Chips are the entities to be assigned to chip
sites on the substrate. Chips contain pins for
interconnection by physical wires to form signal sets. In
this study, the pins on the chips are ignored and the
distance is measured from the center of the chip. Hence,
a signal set becomes a subset of chips, and a signal set
specification defines the interconnection of all chips on
a specific substrate. The routing length is defined as
half-perimeter of the smallest rectangle, which encloses
the chips in the signal set.
The failure rate of a chip is estimated using the
Arrhenius relation as:
E  1
1 
 (Ti )   (Tr )  exp  a   
 B  Tr
Ti 
(1)
where (Ti) and (Tr) are the failure rates of the chip at
a temperature of Ti K and at a reference temperature of
Tr K, respectively; Ea is the activation energy (eV); B is
the Boltzmann's constant. To determine the failure rate
of an individual chip, various operating parameters
need to be specified. Without loss of generality, in this
study, all chips are assumed to be the same factors of
(Tr) and Ea, which are 1 Fit (i.e. 10-9/hour) and 1 eV,
respectively. The system failure rate of an MCM is
given by the sum of the individual chip failure rates.
The placement problem can be formally stated as
follows: given a set of chips {ci 1  i  m} with its set
of heat dissipations {qi 1  i  m}, a set of chip sites
on the substrate, {si 1  i  t}, and a netlist
interconnecting chips and I/O pads, assign each chip to
one of the chip sites such that the total routing length
(TRL) and system failure rate (λ) are minimized. In
the study, I/O pads are considered as fixed chips.
3. FORCE MODELS
Force-directed
technique
is
accomplished
numerically by developing interactive forces between
chips. These forces are created by the designer through
defining connections between chips. In terms of
wireability, a popular force model, namely
interconnection force model, is that each chip exerts
forces of attraction on chips connected by signal nets,
and repulsive forces are used to keep chips apart for
those that are not connected [4-6]. More recently, a
force model for optimizing reliability is presented in
[7-8]. In this study, a hybrid model is developed by
coupling the two different types of force models.
3.1 Interconnection force model
Chips that are highly interconnected need to be
placed close to each other. One might say there is a
force pulling these chips toward each other. Thus, the
number of interconnection between two chips is related
to a force attracting them toward each other. The
interconnection force between two chips ci and cj can
be expressed as
f ijC  k ij  d ij
(1)
where kij is a weighted sum of the nets between the two
chips and dij is a vector directed from ci to cj. The
magnitude of this force is the Manhattan distance
between the two chips. That is, d ij  xij  y ij . It is
needed to point out that an I/O pad is considered as a
fixed chip in the study.
On the other hand, there is a repulsive force
between a pair of unconnected chips. The force is
inversely proportional to the Manhattan distance
between the two chips. The coefficient of the repulsive
force between ci and cj is defined by
0, for either i  j or k ij  0


rij  1 n n , otherwise
 k ij
 U  Cr i
1 j1
(2)
m
Fz CM   Fz iC
m
(3)
(4)
i 1
Once Fz CM is calculated, the force equation is
subtracted by the portion of the center of mass forces.
Then, the force equations become
m
z ij  Fz CM

Fz iC    - k ij  z ij  rij 
 m
d
j=1
ij


(5)
for every movable chip ci.
3.2 Thermal force model
More recently, a thermal force model based on the
heat conduction analogy is presented in [7, 8]. In the
model, the real substrate with chips is firstly
transformed to an unbounded substrate with an infinite
number of chips. Then, each chip pushes the other
chips with forces, named thermal forces. The thermal
force exacted on ci caused by cj is expressed as
f ijT  
qj
(6)
rij 2
2
2
where rij  x ij  yij .
The force in z-direction then is
fz ijT  
qj
rij
2

z ij
in z-direction
(7)
rij
Expanding the formulations to covers all chips in
the unbounded substrate, the net thermal-force exerts
on ci in z-direction can be formulated as
m
Fzi  
T
where U is the number of unconnected pair, Cr is a
controlling parameter, and n is the number of chips.
The interconnection force exerted on every
movable chip ci in z-direction can be formulated as

z ij 

Fz iC    - k ij  z ij  rij 

d ij 
j 1 
In the study, ‘z’ is used to denote x or y for simplifying
the formulation. The interconnection force exerted on a
fixed chip is set to zero.
In addition, it is also desirable to have the center
of all chips be in the geometric center of the layout
plane so that the placement of chips is balanced.
Physically, it is equivalent to have the forces acted
upon the set of all chips being removed. The force on
the center of mass, denoted by Fz CM , is calculated by
the following equations:


  fz ijT r, c
(8)
j1 r   c  
where (r, c) represents the image chip of cj in the
r-c-substrate [7, 8].
3.3 Hybrid force model
For coupling reliability and wireability needed,
one can combine the force model based on
interconnection and the one based on heat flux to a new
one. Therefore, the hybrid model is defined as
Fz i    Fz iT  (1   )  Fz iC
(9)
for every movable chip ci, where  is the weighting
factor, which is restricted to the range 0    1,
representing the relative importance of the optimization
criteria.
4.
Table 1
Modules Nets
PLACEMENT PROCEDURE
The placement procedure consists two phases:
Phase I being the “zero-force placement,” and Phase II
being the “chip assignment”.
4.1 Zero-force placement
The stage begins with generating a random initial
placement. A system of force equations defined by (9)
is constructed on the initial placement. A Modified
Newton-Raphson (MNR) method [7] is used to solve
the system of equations to find the zero-force position
of every chip.
4.2 Chip assignment
The zero-force placement usually is physically
unacceptable from either the standpoint that the chips
overlap, or that the technology requires placing the
chips in arrays.
Since zero-force placement gives the relative
positioning of the components, it needs to distort this
positioning as little as possible when assign chips to
chip sites for obtaining the final placement. The
assignment problem can be put in the form as follows.
Let aij be a variable describing the assignment of a
chip cj to a chip site si,
 1, if assign c j to si
a ij  
otherwise
 0,
Table 1 shows the description of the two
benchmark circuits. Since there lacks of the chip power
data of MCC1 and MCC2, the data of chip power in
MCC1 and MCC2 are produced based on the data of
GEMI module [11].
MCM information
Pins
I/O
Pads
Power dissipation value
(power × chip number)
2496
765
25 W×2, 16 W×4
MCC2 7118 14659
548
MCC1
802
A TAMS program developed by Ellison [12] is
used to predict the temperature distributions of chips on
the substrate. Fig. 4 shows a TAMS model of an MCM.
The package consists of a sandwich structure formed
from the ceramic multiplayer substrate-epoxy
adhesive-aluminum heat sink with thicknesses of 9,
0.076, 1.27 mm, respectively. Thermal conductivities
of the substrate, the epoxy layer, and the heat sink are
39.4 W/mK, 0.276 W/mK, and 195 W/mK, respectively.
The average heat transfer coefficients for htop and hbot
are 43.8 W/m2 K and 832 W/m2 K, correspondingly.
Y
w
0
 a ij  1
for j = 1, 2, …, m
(11a)
 a ij  1
for i = 1, 2, …, t
(11b)
i 1
m
j1
The objective is to
t
minimize
m
 rij a ij
h top
(10)
Each chip must be placed, and at any chip site there
cannot be more than one chip. Therefore
t
30 W×15, 27 W×3,
25 W×5, 16 W×9,
13 W×3, 7 W×2
(12)
i 1 j1
This assignment problem is solved by the Hungarian
method [9].
5. COMPUTATIONAL RESULTS
The proposed algorithm was implemented in C on
a 1.7GHz Pentium IV personal computer. We test it on
two benchmarks: MCC1 and MCC2 [10].
Epoxy

Multiplayer
substrate
Heat sink
X
h bot
Fig. 1 Multiplayer thermal model for an MCM
The placement procedure is applied to both
examples for the convection cooling models using
weighting factors, ω, of 0, 0.1, 0.2, …, 1.0. The
placement results for MCC1 and MCC2 are depicted in
Figs. 2 and 3, respectively. In these figures, the TRL
and the system failure rate (λ) are defined as the
normalized values. Basically, increasing the weighting
factor has the expected effect of decreasing the system
failure rate and increasing the total routing length.
However, when the weighting factor is small, the trend
is not satisfied in MCC2. It is also noticed that several
cases of different values of ω in Fig. 2 have the same
placement results. It is because that MCC1 includes
only six chips. Furthermore, for MCC2, the optimal
placement for wireability is not at the case of ω=0 but
at the case of ω=0.3. This phenomena need further
study.
plot(w,x1,'o-',w,y1,'dr-');
axis([0 1 -0.1 1.1])
xlabel('\fontsize{18}\omega');
ylabel('\fontsize{18}Normalized TRL or \lambda');
legend('\fontsize{18}TRL', '\fontsize{18}\lambda')
6. CONCLUSIONS
Fig. 2
Placement results for MCC1
x1=([19014 19014 19812 19812 19812 19812 19812
20813 23936 23985 26057]-19014)/(26057-19014);
y1=([183707 183707 177298 177298 177298 177298
177298 167616 163861 163861
163861]-163861)/(183707-163861);
w=[0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1];
The methodology for chip placement presented
here is based on minimizing the system failure rate and
on minimizing the total routing length. The coupling is
achieved through use of a hybrid force model that is a
combination of an interconnection force model and a
thermal force model. The layout designer can place
chips for either reliability or wireability by managing
the selected weighting factor. Basically, increasing the
weighting factor has the expected effect of decreasing
the system failure rate and increasing the total routing
length. However, when the weighting factor is small,
the trend is not satisfied.
ACKNOWLEDGMENT
This work was supported by the National Science
Council under contract no. NSC 90-2215-E-218-004.
REFERENCES
plot(w,x1,'o-',w,y1,'dr-');
axis([0 1 -0.1 1.1])
xlabel('\fontsize{18}\omega');
ylabel('\fontsize{18}Normalized TRL or \lambda');
legend('\fontsize{18}TRL', '\fontsize{18}\lambda')
Fig. 3 Placement results for MCC2
x1=([667604 653287 671359 637749 657329 680514
696899 719138 730557 756164
1143306]-637749)/(1143306-637749);
y1=([126945 146444 136252 131079 127032 92339
66989 60237 55050 52253
47459]-47459)/(146444-47459);
w=[ 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1];
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