Hybrid Optical/Digital
Processor for Radar Imaging
23 September 2003
Keith Frampton
Essex Corporation
9150 Guilford Road
Columbia, MD 21046
301-953-7875
Frampton@essexcorp.com
Pat Stover
Annapolis Micro Systems
190 Admiral Cochrane Dr. Suite 130
Annapolis, MD 21401
410-841-2514
Patrick.stover@annapmicro.com
Problem Statement and Solution
• Problem:
– Projected BMD threat environment will have clutter and EMI
– LFM waveforms have limitations with these threats
– Desired advanced waveforms (chaotic, PRN*, …) are very
processing intensive
• Solution:
– The advanced optical processor (AOP) generates
range-Doppler images from advanced arbitrary waveforms
– AOP architecture incorporates:
•Embedded optical signal processing
•Embedded digital signal processing in FPGAs
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Program Objectives
• Modernize the architecture, scaling to:
–
–
–
–
1 GHz
Real-time operation
Full complex, single pass
Store images in real-time to disk
• Compact rack stackable configuration
Power Supplies
6U Card Cage
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AOP 2 Performance Characteristics
Pulse Width
10 msec to 50 msec
Pulse Repetition Interval (PRI)
Pulse Repetition Frequency (PRF)
100 usec minimum
10 kHz maximum
Center Frequency
Tunable 5 GHz to 7 GHz (TBR)
Bandwidth (-3dB)
1 GHz
Stable Reference Frequency
10 MHz
Post-Compression Dynamic Range
(peak to RMS noise)
66 dB
Spur Free Dynamic Range
85 dB for 128 coherently integrated pulses
Range Resolution
0.15 meters
SNR Loss vs. Range center
6 dB maximum @ +/- 76.7 meters relative to
image center
Range Bins
1024 bins (+/- 512 about image center)
Range Extent
153 meters (+/-76.7 m about image center)
Range Sidelobes (Hamming weighting)
-34 dB
Frequency Response
3 dB uncorrected; 1 dB corrected
RCS Repeatability
+/- 0.1 dB
Phase Deviation from Linear in CPS
+/- 5 degrees
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Algorithm Functionality is Similar
Digital Implementation
Radar
Return
A/D
Presum
X
Radar
Reference
Compressed
in Doppler
Compressed
in range
FFT
FFT
IFFT
FFT
Range-Doppler
Map
X
Equalization
Dig_96.CVS
Optical/Digital Implementation
Radar
Return
Compressed
in range
Optical
FT
X
Radar
Reference
Optical
FT
Sum
A/D
X
IFFT
FFT
Compressed
in Doppler
Range-Doppler
Map
Equalization,
weighting,
compensation, &
non-linear ops.
optical domain
digital domain
OPT_97.CVS
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Process Flow
Return
Cross power
spectra vs. time
Tim e, t
STCS(f,t)
Radar Bandwidth
(Frequency, f)
PP(t,)
Complex
Ra nge
Doppler
Data
Range, 
pulse
compression
Tim e, t
Reference
Digital Signal
Processing Unit
(2D FFT)
Acousto-Optic
Unit
(1-D FFTs)
Correlator
compresses
pulse in range
(1-D FFTs)
CAF(  )
Doppler, 
S = spectrum of radar return signal
R = spectrum of radar reference signal
Frequency of each fringe is
proportional to range.
Phase change over time is
proportional to Doppler.
FFT
compresses
pulses in
Doppler
Range, 
PROCFLW2.CVS
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AOP2 Functional Configuration
AOP2 Radar Receiver
Radar
Return
Signal
Radar
Reference
Signal
RF
Front
End
Optics
Camera
Electronics
Real-time
Signal
Processing
Hardware
Image Selection
•Range
•Range-Doppler
•Range-Velocity*
19” Rack-mountable 6U card cage
PC
AOP-2
Control
* future capability
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AOP 2 Top Level System Diagram
Ethernet
Radar Transmit
Data
Frequency
Reference
Signal
Generator
Digital Radar
Reference
(Functional)
Radar
Compressed
Images
(future)
Controller
VMIC SBC
Windows 2000
C++, Labview,
Java
Tektronix
AWG710
Fibre
PMC
RF Signals
VME64
Synchronize Trigger
Timing & Control
RF
Front-End
AO
Modular,
Signals
Connectorized
Components
Radar
Return
HEPC 2003 September 23, 2003
Processing &
Control
Optics
Custom, Harris
for Packaging
Camera
Data
AMS, FPGA
based
Fibre
card
Fibre
Disk
External
Triggers
8
Radar Configuration with AOP2
Radar Return
Signal
Radar
Transmit /
receive
RF
Radar Transmit
Signal
Waveform
generators
Std.
Receiver
Discrimination
and Data Post
Processing
Target
Information
AOP 2
Receiver
Radar
Reference
Signal
All part of AOP 2
HEPC 2003 September 23, 2003
Rangecompressed
Image
Real-time
Disk
Range-compressed or
Range-Doppler Images
Future real-time interface
9
Full Complex, Wideband Architecture
Doppler
AOP2 Configuration
Range
Cross Power Spectra
Complex
data
Photosensor Array
(2048 x 4)
Fourier
Transform
Optics
Acousto Optic
Modulator (AOM)
Laser
+
-
I
+
-
Q
Raster Detector
Output vs. Time
2D FFT
(DSP)
RangeRangeDoppler
Doppler
Map
Image
(CAF)
s(t) {Analog radar return signal}
r(t) {Analog radar reference}
Analog (RF) Input (No A/D)
Arbitrary waveforms
Digital output
Real-time processing
Small size, weight and power
Full complex images
Aegis1.CVS
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Optics Module Mated With Camera Module
Optics Module
Optics Processing Module
Camera Card
Bragg Cell SMA Connectors
Optics Module Connector
Camera Card Connectors
6U VME form factor
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AOP2 Optics Module
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System Calibrations and Corrections
• Calibrations and corrections are required at various
points in the processing chain
– Correct radar and processor response
– Obtain optimum performance
RF Bragg
data
Camera data
I/Q data
CPS x phase
CPSI, CPSQ
(2, analog)
(2048, 4)
(2048, 2)
Range
compressed
images
RCII, RCIQ
(2048, 2)
Return
Reference
RF Front
End
Channel power
Optical
CPS
I/Q
Combine
Amplitude weighting
Range
Compression
FFT
Line phase correction
Range roll-Off
Deconvolutional filter
Range scale
Amplitude scale
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AOP2 Hardware Configuration*
Waveform
generators
• Reference
• Return
6U card cage
Programmable
LOs for
tunable RF
front-end
- Controller card
- Optical module
- Post processing & Timing card
Real-time file
system
Power Meter
RF module
UPS
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Power amplifiers
* Including test equipment
14
AOP Production Conceptual Configuration
Size reduced from ½ rack in AOP2
demonstration to ½ single 6U
chassis:
• AWGs reduced to single chip
for PRN codes
• Synthesizers reduced to
fixed LOs
• Amplifiers reduced to single
card
• No output data storage, data
sent to radar post
processing in real time
Optical
Receiver RFFE Amps
Waveform generators
Amplifiers
RF front-end & LOs
Optical receiver
Camera & timing
Processing & control card
Controller
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Post Processing & Control Subsystem (PCS)
Wildstar II VME
172
Bridge
Virtex II
PE1
PE2
Virtex
Virtex II
II
PE1
PE0
Virtex
Virtex II
II
172
6U Card
88
Backplan
e I/O P2
SBC: Host
Processor
Camera
Control
VME64
Disk
PE1
PE1
Virtex II
Virtex II
172
88
Backplan
e I/O P0
VME to PCI
Bridge
Camera Digital
Data In
Fibr
eDis
k
168
RF & Signal Generator
Quad Fibre
Channel 2 I/O
2-3 6U Cards
Monitor
HEPC 2003 September 23, 2003
Radar
Compressed
Images
16
PCS External Interfaces
AWG
Camera
Controller
1AWG[1:0]
2AWG[1:0]
1AWG_ld, 2AWG_ld
1AWG_trig, 2AWG_trig
AWG_mrk
RF
Pixel data A(12)
Pixel data B(12)
Pixel Tap A
Pixel Tap B
Pixel data C(12)
Pixel data D(12)
Pixel Tap C
Pixel Tap D
Pixel data E(12)
Pixel data F(12)
Pixel Tap E
Pixel Tap F
Pixel data G(12)
Pixel Tap G
Pixel data H(12)
Pixel Tap H
P_CLK
1Attn[5:0]
1Attn[5:0]
2Attn[5:0]
2Attn[5:0]
SW1, SW2[2:0]
Vsync, Hsync
C_trig
SW1, SW2[2:0]
LD_current[7:0]
PD_current[7:0]
R Trig
TEC_actual[5:0]
T Trig
Optical
Module
Range gate Trigger
Transmit Trigger
5V-3V
Interface
Signals that are
connected with cables.
HEPC 2003 September 23, 2003
Processing &
Control Subsystem
VME backplane
signals
Signals using VME
user defined pins
External Signals
17
Annapolis Micro Systems Wildstar II
FPGA based reconfigurable computing board
WILDSTARTM II for VME
Backplane I/O
P0
I/O #0
Flash
Flash
88
168
16
PE 0
VIRTEX TM II
XC2V 6000, 8000
DDR2 36
SRAM
2, 4 MB
32
DDR
SDRAM
64 MB
I/O #1
172
88
168
Flash
16
DDR2 36
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
Backplane I/O
P2
36
DDR2
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
PE 2
VIRTEX TM II
XC2V 6000, 8000
172
3
32
Prog
Osc
DDR2
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
DDR2 36
SRAM
2, 4 MB
172
32/64 Bits
PCI
Controller
DDR
SDRAM
64 MB
32
33/66 MHz
16
PCI to VME Bridge
PE 1
VIRTEX TM II
XC2V 6000, 8000
32
Prog
Osc
32
Flash
Differential
Single Ended
36
3
DDR
SDRAM
64 MB
32
32
16
36
DDR2
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
3
Prog
Osc
32
Master
Clock
Generator
PCLK
MCLK
ICLK
Copyright Annapolis Micro System s, Inc. 2002
VME BUS
HEPC 2003 September 23, 2003
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WILDSTARTM II for VME & Fibre Channel 2 I/O Card
WILDSTARTM II FPGA card
HEPC 2003 September 23, 2003
Fibre Channel 2 I/O Card
daughter card
19
Internal PCS Interfaces
Raw Camera Data
PE0
PE1
PE2
• Compute
Range/Doppler
Image
• Collect Raw Data
from detector
CPS
I&Q
• Compute Range
Compressed
Image
• Apply Correction
Fibre Disk
• Combine to get I
&Q
CPS
RCI or
Range/Doppler
• Update status for
Controller
• Apply Correction
to get CPS
CPS
• Apply Correction
to RCI
RCI
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PE2 Data Processing
VME64
Camera CLK
H_sync
V_sync
Trigger
System
Controller
Camera
Controller
Signal Generation &
RF Front End Signals
Amplitude
Weighting
Memories
Control
signals
PA(11:0)
PB(11:0)
X
PC(11:0)
PD(11:0)
X
Pixel Data
Memories
X
PE(11:0)
X
PF(11:0)
PG(11:0)
PH(11:0)
I+(15:0)
-
I(15:0)
I-(15:0)
Complex
Data
Q+(15:0)
-
Q(15:0)
Q-(15:0)
I+(11:0)
I-(11:0)
Q+(11:0)
Raw Data
Q-(11:0)
Internal
HEPC 2003 September 23, 2003
Signal Generation and RF Front End
PCS
Optical
Module
Controller
21
PE2 Allocated Memory Diagram
Backplane I/O
P0
Flash
88
Internal RAM: 16KB allocated
iAmpWtTbl – 8192B
qAmpWtTbl – 8192B
Backplane I/O
P2
88
16
36
DDR2 36
SRAM
2, 4 MB
iRawPixelData – 2MB
PE 2
VIRTEX TM II
XC2V 6000, 8000
DDR2 36
SRAM
2, 4 MB
iCalRawPixelData – 8KB
DDR2 36
SRAM
2, 4 MB
36
36
DDR2
SRAM
2, 4 MB
qRawPixelData – 2MB
DDR2
SRAM
2, 4 MB
qCalRawPixelData – 8KB
DDR2
SRAM
2, 4 MB
Direct connect to PE 0
Direct connect to PE 1
172
32
3
DDR
SDRAM
64 MB
Flash
Differential
Single Ended
172
Prog
Osc
PCI
Controller
16
PCI to VME Bridge
Master
Clock
Generator
PCLK
MCLK
ICLK
Copyright Annapolis Micro Systems, Inc. 2002
VME BUS
HEPC 2003 September 23, 2003
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PE1 Functional Flow Diagram
iCorrectedPreFFT
PE2
iData(15:0)
qData(15:0)
dataSrcPE1
qCorrectedPreFFT
Select
Data
Source
iPixelData
qPixelData
memClearPE1
Is memory full?
no
Write Data to
Memory
yes
updatedLPCorr
linePhErrMeas
Apply Line Phase
Correction
decvFiltWdwVect
Apply
Deconvolutional
Filter and FFT
Window
upLP(0)
PE0
upDF(0)
updatedDeconv
Is memory full?
no
Write Data to
Memory
yes
FFT Processing
iRngImgData(31:0)
qRngImgData(31:0)
PE2
HEPC 2003 September 23, 2003
cpsData(31:0)
Interleave I,Q
PE0
23
PE1 Allocated Memory Diagram
Internal RAM: 24KB allocated
linePhErrMeas – 8192B
decvFiltWdwVect – 8192B
rangeRollOffVect – 8192B
I/O #1
172
168
Flash
16
Direct connect to PE 0
36
DDR2 36
SRAM
2, 4 MB
DDR2
SRAM
2, 4 MB
iPixelData – 1MB
qPixelData – 1MB
PE 1
VIRTEX TM II
XC2V 6000, 8000
DDR2 36
SRAM
2, 4 MB
36 DDR2
SRAM
2, 4 MB
iCorrectedPreFFT – 1MB
qCorrectedPreFFT – 1MB
DDR2 36
SRAM
2, 4 MB
36
DDR2
SRAM
2, 4 MB
iRngImage – 2MB
qRngImage – 2MB
172
32
Direct connect to PE 2
3
Prog
Osc
DDR
SDRAM
64 MB
32
32/64 Bits
Flash
PCI
Controller
16
PCI to VME Bridge
VME BUS
HEPC 2003 September 23, 2003
32
33/66 MHz
Master
Clock
Generator
PCLK
MCLK
ICLK
Differential
Single Ended
Copyright Annapolis Micro Systems, Inc. 2002
24
PE0 Functional Diagram
PE1
Range
Data
iRngImgData (31:0)
qRngImgData (31:0)
dataSrcPE0
Register
Deinterleave
Data
Calculate
Memory
Address by
Row
Calculate
Memory
Address by
Column
Doppler
FFT
Read
Static
Memory
2&3
rngRollOffVect
Read
LADMux
Block Ram
Read
Static
Memory
0&1
iRng
qRng
RngDoppImage
(I & Q)
Write to
Dynamic
Memory
memClearPE0 1
Constant
Interleave
Data
0
Multiply
Data By
Range Roll-Off
Vector
Calculate
Memory
Address by
Column
Read
LADMux
Block Ram
doppFFTWdw
PE2
CPS
Data
Terminate
icpsData (31:0)
qcpsData (31:0)
Calculate
Memory
Address by
Row
Multiply
Data By
Doppler
Window
Write to
Static
Memory
0&1
Write to
Static
Memory
2&3
PE1
Cal
1
upLP (0)
upDF (0)
memClearPE0
Constant
1
Write to
Static
Memory
4&5
iRngDoppData (31:0)
qRngDoppData(31:0)
iRngImage
qRngImage
procMode
Constant
Sift
iImageData (31:0)
qImageData (31:0)
HEPC 2003 September 23, 2003
0
pulseHeader (63:0)
0
Terminate
Make
Cycle
Cnt/Cal
Header
First
Data
in Pulse
Fibre
Disk
25
PE0 Allocated Memory Diagram
I/O #0
Flash
Direct connect to PE 1
172
168
16
iRng0 – 2MB
DDR2 36
SRAM
2, 4 MB
iRng1 – 2MB
DDR2 36
SRAM
2, 4 MB
iRngDoppImage – 2MB
PE 0
VIRTEX TM II
XC2V 6000, 8000
DDR2 36
SRAM
2, 4 MB
32
Internal RAM: 2KB allocated
iDoppFFTWdw – 1024B
qDoppFFTWdw – 1024B
DDR
SDRAM
64 MB
36
DDR2
SRAM
2, 4 MB
qRng0 – 2MB
36
DDR2
SRAM
2, 4 MB
qRng1 – 2MB
36
DDR2
SRAM
2, 4 MB
qRngDoppImage – 2MB
172
3
Direct connect to PE 2
Prog
Osc
32
32
32/64 Bits
Flash
RngDopp – 8MB
Differential
Single Ended
PCI
Controller
16
PCI to VME Bridge
Master
Clock
Generator
PCLK
MCLK
ICLK
Copyright Annapolis Micro Systems, Inc. 2002
VME BUS
HEPC 2003 September 23, 2003
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Corefire Example
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PCS Testing: CoreFire Debugger
CoreFireTM Application Debugger includes windows for
monitoring and manipulating data flow
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Wildstar II FFT Example
FFT Example Scenario
• CoreFire project for PE1
Data read from memory on Wildstar II board
FFT operation
Data written to memory on Wildstar II board
• Java program
Data read from file
Data written to memory on Wildstar II board
Data read from memory on Wildstar II board
Data written to file
• CoreFire Debugger
Kicks off the Wildstar II board processing
Memory and register viewers show data
during the processing
• IView Tool
Compare output data file with
expected results
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Wildstar II FFT Example
FFT done on
Wildstar board
FFT done in SW
Scale and Subtract
(Magnitude)
Peak to RMS = 139 dB
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Conclusions
• Essex has been able to implement an extremely
complex, computationally intensive radar processing
task in:
– Embedded optical hardware and
– Embedded DSP/FPGA hardware
• This approach saves space, development time,
software, development costs and maintenance costs.
• The AOP hardware allows the use of new arbitrary
classes of waveforms for improved ballistic missile
discrimination.
HEPC 2003 September 23, 2003
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Wrap-up / Questions
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