DMB Production
8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board
550 Production Boards
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
1
DMB Production Boards
- 411/550 boards delivered/tested
- 70 boards required repair
Board are being boxed and stored
until needed at Ohio State
Production Schedule
Jan Feb M ar Apr M ay
DMB
350 450 550
TMB-RAT
10*
CCB
10 20 40
MPC
10
LVRB
10 20 40
Backplane
4*
Controller
10 20 40
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
2005
Jun Jul Aug Sep Oct Nov Dec
60
20
60
60
30
70
40
70
10
70
150 270 390 510
60
70
20
40
60
540
70
2
New Crate Controller Development
A VMEbus Controller with Gigabit
Ethernet
–
–
–
–
–
A custom board designed and
developed at OSU
Based on XILINX Virtex-II Pro
Custom firmware.
Optical transceiver (for Gbit Ethernet)
Communicates with stand-alone PC
(in USC55) via Gigabit Ethernet
It’s Alive !
Measured: Continuous Read/Write
VME Transfers at 120 Mbit/s
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
3
Gigabit-VME Ethernet Protocol
Utilize Commercial Software (Drivers)
Ethernet Raw Socket Layer (requires setuid();)
Packet to Controller:
Ethernet Header
Private Protocol Header
Dest Addr | SRC Addr | PktLen
14 bytes
PktType | NVME
VME Write 1
Cntrl | VME Addr | Data
4 bytes
VME Read 2
Cntrl | VME Addr
8 bytes
6 bytes
VME Delay 3
Cntrl | VME Delay
VME Write 4

Cntrl | VME Addr | Data
4 bytes
8 bytes
Packet from Controller:
Ethernet Header
Dest Addr | SRC Addr | PktLen
14 bytes
Private Rcv. Header
PktType | RSVD | NWrds
6 bytes
Data from VME
Data
Data
Data
…
Data
Data
Data
Data
Data
Data
Data

2 bytes 2 bytes …
Note: Jumbo Packet Support 9000 bytes
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
4
Controller Production Schedule
New Controller has Run in DDU/DCC Crate for 1 Month
- Very Stable, No Bus Hangs or Resets Needed Yet!
- 2nd prototype/preproduction board TBD (some changed
components, layout fixes, and form factor change)
- Radiation Tests Need to be Performed
Firmware Additions Needed:
- Storage of MAC Address in Flash RAM
- Controller Handshake for Overflow Protection
- JTAG interface for reprogramming PROM via ethernet
Production Schedule
2005
Jan Feb M ar Apr M ay Jun Jul Aug Sep Oct Nov Dec
DMB
350 450 550
TMB-RAT
10*
30 150 270 390 510 540
CCB
10 20 40 60 70
MPC
10 20 40 60 70
LVRB
10 20 40 60 70
Backplane
4*
10 20 40 60 70
Controller
10 20 40 60 70
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
5
DDU Prototype
FMM
output
port
• Functions
– Merge data from 13 DMBs
– Perform error checking
and status monitoring
VME
FPGA
(CRC, word count,
L1 number, BXN,
overflow, link status)
Optical
Fiber
Input (15)
Input
FPGA
Main FPGA
GbE
To Local
DAQ
SLINK
Mezz Board
GbE
FIFO
Input
FIFOs
– Communicates w/FMM
• Large Buffer Capacity
– 2.5 MB buffer
– Average DDU data volume
estimated to be 0.4kB per
L1A at LHC (@1034 lumi)
– Buffer can hold over
6000 events
• TTC signals from DCC
• Slow control via VME
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
6
DCC Prototype
VME
SLINK
Output
FIFOs
Input
FIFOs
Input
FPGAs
TTCrx
Control
FPGA
SLINK
J1 backplane
DDU
data
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
• Data Concentration
– Merge data from 9 DDUs
– send merged data to
central DAQ via 1 or 2
SLINKs
– Has two optional GbE
spy data path
• Fast Control
– Receive TTC fiber signals
using TTCrx,
– Fanout L1A, LHC_clock
and other TTC signals to
DDUs
– Has optional FMM
interface
7
DDU/DCC Prototype
DDU/DCC TestBeam 2004
- very successful, no problem for > 10x LHC rate
Both DDU/DCC Passed ESR Nov. 2004
DDR FIFO bit errors – bad chip used on DDU/DCC/Controller (72T40/20 family)
Qout[39:20]
•
IDT72T40118, 40-bit 0.5MByte, DDR FIFO
bit errors, esp. bit 21
•
Detailed test on test board
•
Error shown on DDU and VME_controller
(DDR FIFO)
•
Still working with IDT
•
Replacement:
TI SN74V3690
IDT 72V36110
D[39:20] Q[39:20]
LFSR Din[19:0]
parity
FIFO
D[19:0]
Q[19:0]
FIFO
Write/read
COMP
Qout[19:0]
Error
report
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
8
DDU/DCC Production
baseline
Relayout Both DDU and DCC
Detector Dependent Unit (DDU)
9/crate, 50 will be built
Data Concentration Card (DCC)
1 or 2/crate, 10 will be built
Production Schedule
C
O
N
T
R
O
L
L
E
R
DD D D D D D D D D
DD D D D C D D D D
UU U U U C U U U U
optional
D
C
C
( * : pre-production boards)
2005
Jan Feb M ar Apr M ay Jun Jul Aug Sep Oct Nov Dec
DDU
10*
30 50
DCC
2*
6
10
Backplane
1
4
5
Controller
1
4
5
S. Durkin, CMS EMU Meeting U.C. Davis Feb. 25, 2005
9