VM Design Issues
Vivek Pai / Kai Li
Princeton University
Mini-Gedankenexperimenten
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What’s the refresh rate of your monitor?
What is the access time of a hard drive?
What response time determines sluggishness
or speediness? What’s the relation?
What determines the running speed of a
program that’s paging heavily?
If you have a program that pages heavily,
what are your options to improve the
situation?
2
Mechanics
Let’s finish off last lecture
 Memory mapping, Unified VM next time
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Mid-term on track
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No assigned reading yet, may not exist
Covers everything before it
Open Q&A session?
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Is there interest?
If so, when?
3
Where We Left Off Last Time
Various approaches to evicting pages
 Some discussion about why doing even
“well” is hard to implement
 Belady’s algorithm for off-line analysis
 We just finished variations on FIFO
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In particular, enhanced FIFO with 2nd
chance
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Lessons From Enhanced FIFO
Observation: it’s easier to evict a clean
page than a dirty page
 2nd observation: sometimes the disk
and CPU are idle
 Optimization: when system’s free, write
dirty pages back to disk, but don’t evict
 Called flushing – often falls to pager
daemon
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5
Least Recently Used (LRU)
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Algorithm
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Replace page that hasn’t been used for the
longest time
Question
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What hardware mechanisms required to
implement LRU?
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Implementing LRU
Mostly
recently used
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5 3 4 7 9 11 2 1 15
Least
recently used
Perfect
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Use a timestamp on each reference
Keep a list of pages ordered by time of
reference
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Approximate LRU
Most recently used
Least recently used
LRU
N categories
pages in order of last reference
Crude
LRU
8-bit
count
2 categories
pages referenced since
the last page fault
pages not referenced
since the last page fault
0
...
1
2
3
254 255
256 categories
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Aging: Not Frequently Used (NFU)
00000000
00000000
10000000
00000000
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10100000
01010000
00111000
01000000
Shift reference bits into counters
Pick the page with the smallest counter
NFU has a short history (counter length)
How many bits are enough?
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01000000
10100000
01110000
10000000
Main difference between NFU and LRU?
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10000000
01000000
11100000
00000000
Algorithm
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00000000
10000000
11000000
00000000
In practice 8 bits are quite good
Pros: Require one reference bit
Cons: Require looking at all counters
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Where Do We Get Storage?
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32 bit VA to 32 bit PA – no space, right?
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No need to store offset
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Offset within page is the same
4KB page = 12 bits of offset
Those 12 bits are “free” in PTE
Page # + other info <= 32 bits
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Makes storing info easy
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x86 Page Table Entry
Page frame number U P Cw Gl L D A Cd Wt O W V
31
12
Reserved
Valid
Writable
Owner (user/kernel)
Write-through
Cache disabled
Accessed (referenced)
Dirty
PDE maps 4MB
Global
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What Happens on Diagonal Lines
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My screen is 1024*768 pixels
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256 colors = 1 byte per pixel = .75MB
64K colors = 2 bytes/pixel = 1.5MB
Page size is 4KB
Screen is 192 or 384 pages
1 page = several horizontal lines
 Diagonal/vertical lines = TLB badness
 “Superpages” to the rescue
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The Big Picture
We’ve talked about single evictions
 Most computers are multiprogrammed
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Single eviction decision still needed
New concern – allocating resources
How to be “fair enough” and achieve good
overall throughput
This is a competitive world – local and
global resource allocation decisions
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Program Behaviors
80/20 rule
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Locality
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> 80% memory references
are made by < 20% of
code
Spatial and temporal
# page faults
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Working set
Working set
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Keep a set of pages in
memory would avoid a lot
of page faults
# pages in memory
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Observations re Working Set
Working set isn’t static
 There often isn’t a single “working set”
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Multiple plateaus in previous curve
Program coding style affects working set
Working set is hard to gauge
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What’s the working set of an interactive
program?
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Working Set
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Main idea
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Keep the working set in memory
An algorithm
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On a page fault, scan through all pages of the
process
If the reference bit is 1, record the current time
for the page
If the reference bit is 0, check the “last use time”
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If the page has not been used within d, replace the page
Otherwise, go to the next
Add the faulting page to the working set
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WSClock Paging Algorithm
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Follow the clock hand
If the reference bit is 1, set reference bit to 0,
set the current time for the page and go to
the next
If the reference bit is 0, check “last use time”
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If page has been used within d, go to the next
If page hasn’t been used within d and modify bit is 1
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Schedule the page for page out and go to the next
If page hasn’t been used within d and modified bit is 0
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Replace this page
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Simulating Modify Bit with
Access Bits
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Set pages read-only if they are read-write
Use a reserved bit to remember if the page is
really read-only
On a read fault
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If it is not really read-only, then record a modify in
the data structure and change it to read-write
Restart the instruction
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Implementing LRU without
Reference Bit
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Some machines have no reference bit
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VAX, for example
Use the valid bit or access bit to simulate
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Invalidate all valid bits (even they are valid)
Use a reserved bit to remember if a page is really
valid
On a page fault
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If it is a valid reference, set the valid bit and place the
page in the LRU list
If it is a invalid reference, do the page replacement
Restart the faulting instruction
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Demand Paging
Pure demand paging relies only on
faults to bring in pages
 Problems?
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Possibly lots of faults at startup
Ignores spatial locality
Remedies
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Loading groups of pages per fault
Prefetching/preloading
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Speed and Sluggishness
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Slow is > .1 seconds (100 ms)
Speedy is << .1 seconds
Monitors tend to be 60+ Hz =
<16.7ms between screen paints
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Disks have seek + rotational delay
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Seek is somewhere between 7-16 ms
At 7200rpm, one rotation = 1/120 sec = 8ms.
Half-rotation is 4ms
Conclusion? One disk access OK, six are bad
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Disk Address
Use physical
memory as a
cache for disk
 Where to find
a page on a
page fault?
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Virtual
address
space
invalid
Physical
memory
PPage# field is
a disk address
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Imagine a Global LRU
Global – across all processes
 Idea – when a page is needed, pick the
oldest page in the system
 Problems? Process mixes?
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Interactive processes
Active large-memory sweep processes
Mitigating damage?
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Amdahl’s Law
Gene Amdahl (IBM, then Amdahl)
 Noticed the bottlenecks to speedup
 Assume speedup affects one
component
 New time =
(1-not affected) + affected/speedup
 In other words, diminishing returns
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NT x86 Virtual Address Space Layouts
00000000
Application code
Globals
Per-thread stacks
DLL code
3-GB user space
7FFFFFFF
80000000
Kernel & exec
HAL
Boot drivers
C0000000 Process page tables
Hyperspace
C0800000
System cache
Paged pool
Nonpaged pool
FFFFFFFF
BFFFFFFF
C0000000
1-GB system space
FFFFFFFF
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Virtual Address Space in Win95 and Win98
00000000
User accessible
7FFFFFFF
80000000 Shared, process-writable
(DLLs, shared memory,
Win16 applications)
C0000000
FFFFFFFF
Unique per process
(per application),
user mode
Systemwide
user mode
Win95 and Win98
Operating system
(Ring 0 components)
Systemwide
kernel mode
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Details with VM Management
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Create a process’s virtual address space
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Allocate page table entries (reserve in NT)
Allocate backing store space (commit in NT)
Put related info into PCB
Destroy a virtual address space
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Deallocate all disk pages (decommit in NT)
Deallocate all page table entries (release in NT)
Deallocate all page frames
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Page States (NT)
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Active: Part of a working set and a PTE points to it
Transition: I/O in progress (not in any working sets)
Standby: Was in a working set, but removed.
A PTE points to it, not modified and invalid.
Modified: Was in a working set, but removed.
A PTE points to it, modified and invalid.
Modified no write: Same as modified but no write
back
Free: Free with non-zero content
Zeroed: Free with zero content
Bad: hardware errors
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Dynamics in NT VM
Demand
zero fault
Page in or allocation
Standby
list
Process
“Soft”
working faults
set
Modified
writer
Free
list
Zero
thread
Zero
list
Bad
list
Modified
list
Working set
replacement
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Shared Memory
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How to destroy a
virtual address space?
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How to swap out/in?
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Link all PTEs
Reference count
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.
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.
..
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Page table
Process 1
Link all PTEs
Operation on all entries
How to pin/unpin?
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w
Link all PTEs
Reference count
.
.
.
w
.
.
.
..
.
Physical
pages
Page table
Process 2
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Copy-On-Write
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Child’s virtual address
space uses the same
page mapping as
parent’s
Make all pages read-only
Make child process ready
On a read, nothing
happens
On a write, generates an
access fault
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map to a new page
frame
copy the page over
restart the instruction
r
r
.
.
.
..
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Page table
Parent process
r
r
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.
.
..
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.
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Physical
pages
Page table
Child process
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Issues of Copy-On-Write
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How to destroy an address space
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How to swap in/out?
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Same as shared memory case?
Same as shared memory
How to pin/unpin
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Same as shared memory
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