CAD of Digital VLSI
Dr. Ralph Etienne-Cummings
Exam 2: The Inverter, Combinational and Sequential Logic (1.5 hours, Open book)
November 3, 2004
Attempt all questions. Show all calculations to obtain partial credits. If you run out of time,
outline how you would approach the problem. This exam will be graded out of 100 (i.e. 20 extra
credit points).
Exam #2 (1.5 Hours)
P.1 (35 pts)
A student misunderstands how to design a transmission gate and places the PMOS and NMOS in
series.
(a) What voltages will have to be applied to the gates of the transistors for this
“transmission gate” to work. (5 pts)
(b) What will be the maximum and minimum output voltages. (Show all work.) Plot the
DC characteristics, labeling all important features of the curve. (15 pts)
(c) Derive the expression for resistance of the transmission gate at Vin = Vout = Vmid.
(15 pts)
P.2 (25 pts)
(a) Determine the function(s) which indicates the number of 0’s in a 2-bit input. (5 pts)
(b) Using AND, OR and NOT gates, implement the results of (a). How many transistors
are required for CMOS implementation? (The direct translation.) (10 pts)
(c) Now implement the circuit with pass transistors only. How many transistors does this
implementation require. (10 pts)
P.3 (40 pts)
(a) Consider the function Y = [(AB’+C ) G’]+EF’]D’. Draw the CMOS schematic for
the function. (Assume the inverses are available.) (10 pts)
(b) If all the transistors are implemented with W/L = 1, Kp = Kn, and Vtop = Vton, what
is the value of the logic threshold, VLT for a 1010100 to 0101011 transition. (5 pts)
(c) Which transitions will have the longest and shortest rise and fall times. (5 pts)
(d) What are the longest and shortest rise and fall times. (20 pts)
P.4 (40 pts)
(a) Using any dynamic logic style you like, design a D-flip-flop. (10 pts)
(b) Show how an 8 bit shift register can be implemented with this D flip-flop. (Provide
the architecture shift register.) (10 pts)
(c) Draw the timing diagram, showing the output of the first 3 stages of the register, as
10011010 is serially loaded into the register. (20 pts)