Fall 01 (Updated)

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Name: SS#:

CAD of Digital VLSI

Dr. Ralph Etienne-Cummings

Exam 2: The Inverter, Combinational and Sequential Logic (1.5 hours, Open book)

October 16, 2001

Attempt all questions. Show all calculations to obtain partial credits. If you run out of time, outline how you would approach the problem.

Exam #2 (1.5 Hours)

NMOSFET PMOSFET

K/2 57.2 uA/V 2 19 uA/V 2

VTO

COX

0.74 V

2.5 fF/um^2

CGDO = CGSO 2E-10 F/m

CJ 4.21E-4 F/m 2

-0.93 V

2.5 fF/um^2

2.52E-10 F/m

7.27E-4 F/m 2

CJSW 3.28E-10 F/m 2.65E-10 F/m

P.1 (30 pts)

(a) Design a 3-input NAND gate with the average of the logic threshold voltages at

Vdd/2. (10 pts)

(b) Rank the logic threshold of the transitions starting from the highest to the lowest. (5 pts)

(c) Compute the longest and shortest fall times using the 90% - 10% criterion. (10 pts)

(d) Compute the peak power consumption for your design. (5 pts)

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P.2 (40 pts)

(a)

Derive the Boolean function that counts the number of zero’s in a 4-bit number. (10 pts)

(b)

(c)

(d)

(e)

Draw the schematic of this function using pass transistor logic. (10 pts)

Estimate the speed of operation of your design if all minimum size transistors are used. (5 pts)

Redesign the circuit with Domino Logic gates. (10 pts)

Estimate the speed of operation of the new design if all minimum size transistors are used. (5 pts)

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P.3 (30 pts)

(a)

(b)

(c)

Design an 8-bit shift register with a clear function. (10 pts)

Draw the schematic of one bit-slice of the register. (10 pts)

Draw the timing diagram for the operation of the register. (10 pts)

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