Fakulti:
FAKULTI KEJURUTERAAN ELEKTRIK
Semakan
Tarikh Keluaran
Pindaan Terakhir
No. Prosedur
Nama Matapelajaran: Makmal Mikroelektronik
Kod Matapelajaran : SEW 4722
:1
: 2013
: 2013
: PK-UTM-FKE-(0)-10
SEW 4722
FAKULTI KEJURUTERAAN ELEKTRIK
UNIVERSITI TEKNOLOGI MALAYSIA
KAMPUS SKUDAI
JOHOR
MICROELECTRONICS LABORATORY
Optimization of MOSFET electrical characteristics using TCAD
Tools
Disediakan oleh
Nama
Disahkan oleh : Ketua Jabatan
Nama
: Dr. Shaikh Nasir Shaikh Husin
Tandatangan
Cop
: Pensyarah
: Dr Suhana Mohamed
Sultan
:
:
Tandatangan
Cop
:
:
Tarikh
: 9 September 2013
Tarikh
: September 2013
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1. Project Introduction
As the Integrated Circuits (IC) industry advances into the ULSI era, use of modeling
tools for sub-micron devices has become part and parcel in building up process
architectures. The conventional “trial and error” approach in experimenting with process
and device design is both expensive and time-consuming.
For a fully integrated modeling system, a virtual semiconductor device undergoes
processes like ion implantation, diffusion, etching etc.,to form the MOSFET device
structure. This finished “product” is then exported into a device simulator to “test” its
electrical functionality. After the parameter extraction, SPICE simulation can be activated
to simulate at circuit level, where the devices are connected through interconnects. In this
simulation exercise, the subject of interest is that of the process flow of a typical n-MOS
device and its impact on the electrical characteristics of the device.
2. Theory
2.1 MOS transistor device characteristics
Figure 1: MOS transistor structure showing three dimensional view
From Figure 1, it can be seen that a MOS transistor is essentially a MOS structure with
two overlapping pn junctions on either side of the gate. For a MOSFET device, there are
basically 4 regions of operation: linear, saturation, breakdown and cut-off as shown in
Figure 2.
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2.2 Linear Region
This is the region in which Ids increases linearly with Vds for a given Vgs. Ids can be
expressed as:
(1)
where µ is the mobility of the carriers in the channel, COX is the gate oxide capacitance
per unit area, W/L is the device width-to-length ratio, and Vth is the threshold voltage.
2.3 Saturation Region
From Figure 2(1), it can be seen that Ids no longer increases linearly, as Vds increases to
higher values. Ids in the saturation region can be expressed as:
(2)
showing the independence of Ids on Vds.
2.4 Breakdown Region
This occurs at high values of Vds and is characterized by a super-linear increase of Ids
with increasing Vds. This may occur due to punchthrough or avalanche breakdown.
2.5 Cut-off Region
This occurs at very low values of Vgs (<Vth) and is characterized by extremely low Ids.
The gate IV characteristics are also shown in Figure 2(ii).
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(i)
(ii)
Figure 2 (i) Typical enhancement MOSFET drain current (Ids) drain voltage (Vds) characteristics
with gate voltage (Vgs) as a parameter, showing different regions of device operation; (a) linear,
(b) saturation, (c) cut-off, and (d) breakdown regions
(ii) Typical MOSFET transfer characteristics showing all regions of device operation
3. Short Channel Effects (SCEs)
The gate voltage controls most of the space charge induced in the channel area of a long
channel device during inversion. MOSFET scaling developments are forced to face the
challenges of short channel effect (SCE). SCE is one of the most critical problems of
deep submicron MOSFET devices. SCE has become the main technological barrier as a
MOSFET is scaled down approaching nano scale region. It has caused performance
degradation and altered the electrical characteristics of a device and summarized as
follow threshold voltage roll-off, drain induced barrier lowering (DIBL), high leakage
current, poor subthreshold slope etcs.
4. Subthreshold Leakage Current
A MOSFET operates in the weak inversion (subthreshold) region when the magnitude of
the gate-source voltage is less than the magnitude of the threshold voltage. In the weak
inversion mode, current conduction between the source and the drain (the substreshold
leakage current) is primarily due to diffusion of the carriers. The transistor off-state
current (IOFF) is the drain current when the gate to source voltage is zero. IOFF is affected
by the threshold voltage, channel length, channel width, depletion width beneath the
channel ara, channel/source doping profiles, drain/source junction depths, gate oxide
thickness, supply voltage and the junction temperature. Figure 3 (i) shows the drain
current (IDS) versus gate voltage (VGS) and Figure 3(ii) shows the log IDS-VGS.
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(i)
(ii)
Figure 3: (i) IDS-VGS plotted graph
(ii) inverse IDS-VGS shows the subtreshold slope
The threshold voltage of a MOSFET is reduced with decreasing channel length. The
effects of scaling the channel length on the threshold voltage and subtreshold leakage
current characteristics of a MOSFET are called short channel effects (SCEs). As with
respect to the gate voltage is approximately linear in subtreshold region. The subtreshold
slope, S (mV/decade) can be evaluated by choosing two points in the subthreshold region
of an ID-VGS plotted graph such that the subthreshold leakage current changes by a factor
of 10.
Subthreshold slope defines the inverse slope of log (ID) versus VGS plotted graph, as
shown in Figure 4. The typical value of subthreshold slope is 60 mV/decade. A device
characterized by steep subthreshold slope exhibits a faster transient between off-on states.
Subthreshold slope can be evaluated by equation 3.
𝑆𝑢𝑏𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 𝑆𝑙𝑜𝑝𝑒 =
∆𝑉𝐺𝑆
𝑙𝑜𝑔∆𝐼𝐷
(3)
ION
Figure 4: Subthreshold Slope Calculation
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5. ION/IOFF ratio
Another important parameter in a MOSFET device is the ION/IOFF ratio. As feature
size decreases, static power consumption is a great concern. This can be observed in
the leakage current when the device is turned off or known as IOFF. The IOFF as shown
in Figure 4 may result in high power consumption for devices of large-scale
integrated circuits, such as memory, processors, controllers, communication and
networking circuits, etc. The high power consumption, in turn, can adversely affect
requirements for heat dissipation. Additionally, in the case of some hand-held
products, the integrated circuits with excess leakage may reduce the operating-time
that may be available within a given fixed-energy battery life. Accordingly, there may
be a demand for low-leakage MOSFETs. Meanwhile ION is the maximum drain
current at given gate and drain voltages and it is desirable to obtain high ION for high
current drive applications.
6. Enhancement mode vs. Depletion mode
In most applications, two kinds of NMOS transistors are used; enhancement mode
devices and depletion mode devices. The enhancement mode device has a threshold
voltage Vth greater than 0, and for the depletion mode device Vth is less than 0.
However, the best device for logic circuit application is enhancement mode device
due to its controlled power consumption and easier to turn off the circuit when it is
not in use.
7. Laboratory Tasks
The project is using the Silvaco (Athena-Atlas) as a process and device simulation
tool. The students are required to familiarize themselves with Silvaco in order to
complete the project task end of this laboratory schedule. Therefore, the students are
required to complete the familiarization and project tasks. The flow of a typical n
channel MOSFET Process Simulation is given in Attachment 1 and Attachment 2
(ATHENA command).
i.
Familiarization Task
1. Able to define and analyze the process of an n-channel metal-oxidesemiconductor Field Effect Transistor (NMOS) using ATHENA.
2. Characterize the NMOS device in ATLAS (Ids-Vg and Ids-Vds graph). Extract
the threshold voltage (Vth), ION, IOFF, and subthreshold swing (S).
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ii.
Problem
You have successfully fabricated an n-MOS device for logic gate application and the
device process follows the input file named device_PBL2.in. The device structure is
shown in Figure 5. Your colleague measured the device and found the device
operates in depletion mode of operation as shown in Figure 6. Besides, the device
exhibits poor ION/IOFF ratio of ~1 and subthreshold slope of >1 V/decade. The current
device channel length is 100 nm. Without changing the oxide thickness, you need to
modify the device process in order to obtain device characteristics as shown in Table
1. These requirements are needed to ensure the device performance in logic
applications.
Parameters
Current device
Requirement
Vth [V]
-2
0 V < Vth < 1 V
ION/IOFF
~ 10
> 1 x 106
Subthreshold Slope (SS)[V/dec]
>1
≤ 0.1
Table 1: Current device characteristics and requirements to enhance the device
performance
iii.
Tasks/Approaches
1. Learn and understand the Silvaco’s TCAD software by trying out the examples.
2. Simulate the current processed device in ATHENA and obtain the Ids-Vg plot in
linear and logarithmic as shown in Figure 6 using ATLAS.
3. Modify and vary the current process in ATHENA to observe any changes in the
device characteristics without changing the oxide thickness. Determine the
optimal values.
4. Extract the characteristics of the device structure and do the cross sections on the
device due to parameter changes. The discussion on the analysis should be
included.
Report should be submitted on the 5th week of the lab session to the lab technicians,
Puan Siti Rohani Binti Samiron/Puan Wan Norafiza.
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Figure 5 NMOS Device Structure
Figure 6 Linear Id-Vg plot measured from current processed device
Figure 7 Logarithmic Id-Vg plot measured from current processed device
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