Logic Design
Dr. Yosry A. Azzam

Binary systems
Chapter 1


Agenda
Binary Systems :
Binary Numbers,
Binary Codes,
Binary Logic

ASCII Code (American
Standard Code for
Information Interchange)

Boolean Algebra
(Basic Theorems, Property of Boolean Algebra,
Boolean Functions)

Logic Gates

Readings

Mano: Ch 1 & 2 (until 2-4)

Objectives

Understand Bit & Byte as the foundation of data representation


Understand the Binary
System, it
’ s operations, conversions and negative number representation
Understand the Logic Gates
& Binary Logics, which they based on
3

Data Representation

The complex computer system is built on a
2-states system (on/off) : The Binary System.

Binary system is a 2 base numbering system: 0 and 1

Each 0 and 1 is called
“
BIT
”
(BInary digiT)
4

Bits & Bytes

Bit (0 or 1)

Off/On for positive logic

On/Off for negative logic
Dec (Bin)
 0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)
 7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)
 13 (1101)

14 (1110)
 15 (1111)
5

Bits & Bytes (cont
’ d)

Byte : a group of 8 bits, r epresent :

ASCII characters (1 byte is 1 character)
Refer to ASCII Table p : 23

Unicode

There are other format of data representation discussed later in the course.

A (0100 0001)

B (0100 0010)
 …

Z (0101 1010)
 …

0 (0011 0000)

1 (0011 0001)
 …

9 (0011 1001)
6

Binary Systems

Binary Numbers

Binary Codes

Binary Logic
7

Binary and Decimal Numbers

Binary



1010 = 1x2 3 + 0x2 2 + 1x2 1 + 0x2 0
0, 1, 10, 11
…
Called
“
Base-2
”

Decimal



7392 = 7x10 3 + 3x10 2 + 9x10 1 + 2x10 0
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
…
Called
“
Base-10
”

Octal

Based-8 : (0, 1, 2, 3, 4, 5, 6, 7)

Hexadecimal

Based-16 : (0, 1, 2, 3, 4, 5, 6, 7, 8 ,9 ,A ,B ,C ,D ,E ,F)
8 Reading : Mano. Chapter 1

Binary Systems and Number Base
Conversion:
Decimal Numbers (Base-10):
0,1,2,3,4,5,6,7,8, and 9
Binary Numbers (Base-2):
Two Digits
Ten Digits
0 and 1
0..7
Octal Numbers (Base-8):
Eight Digits
Hexadecimal No. (Base-16):
0,…,9,A,B,C,D,E,F and so on.
16 Digits
9

1.3 Number Base Conversion
( 1): (7392)
10
= 7x10 3 + 3x10 2 +9x10 1 +2x10 0
(2): (1010.011)
2
= 1x2 3 +0x2
+1x2 -2 +1x2 -3 =(10.375)
10
2 +1x2 1 +0x2 0 +0x2 -1
(3): (4021.2)
5
(511.4)
10
= 4x5 3 +0x5 2 +2x5 1 +1x5 0 +2x5 -1 =
(4): Convert decimal 41 to binary, i.e., (41)
10
Solution:
= ( ¿?)
2
10

Divide by 2 Integer quotent
41/2 =20
20/2
10/2
=10
= 5
5/2
2/2
1/2
= 2
= 1
= 0
Remainder Coefficient
+1
+0
+0
+1
+0
+1
1
0
0
1
0
1
LSB
MSB
OR= 101001
11

Divide by 2
41
20
10
5
2
1
0
Remainder
1
1
0
0
0
1
LSB
MSB
 Answer=101001
(5): Convert (0.6875)
10 to binary.
Multiply by 2 Integer quotient fraction Coefficient
0.6875x2
=1 0.3750
1 MSB
0.3750x2
0.7500x2
0.5000x2
=0
=1
=1
 Answer: (0.6875)
10
= (0.1011)
2
0.7500
0.5000
0.0000
0
1
1 LSB
12

(6): Convert decimal 153 to octal, i.e., (153)
10
Solution:
= ( ¿?)
8
Divide by 8 Remainder
153
19
2
0
1
3
2
LSB
MSB
 Answer=231
 (153)
10
= ( 231)
8
13

(7): Convert (0.513)
10 to octal, to seven significant figures
Multiply by 8 Integer quotient fraction Coefficient
0.513x8
0.104x8
=4
=0
0.104
0.832
4
0
MSB
0.832x8
0.656x8
0.248x8
0.984x8
=6
=5
=1
7
0.656
0.248
0.984
0.872
6
5
1
7 LSB
Answer: (0.513)
10
= (0.406517…..)
8
14

(8): Convert decimal 153.513 to octal, since we know that (153)
10
= ( 231)
8 and (0.513)
10
= ( 0.406517)
8
Then (153.513)
10
= ( 231.406517)
8
1.4 Octal and Hexadecimal Numbers
Since 2 3 =8 and 2 4 =16, each octal digit corresponds to three binary digits and each hexadecimal digit corresponds to four binary digits.
Examples: convert the binary 10110001101011.111100000110 to octal.
Answer: (10 110 001 101 011 . 111 100 000 110)
2
= ( 2 6 1 5 3 . 7 4 0 6 )
8 convert the binary 10110001101011.111100000110 to
Hexadecimal
Answer: (10 1100 0110 1011 . 1111 0000 0110)
2
= ( 2 C 6 B . F 0 6 )
16 15

Binary Numbers : Conversions 2

Octal (2 3 = 8)

(10110001101011.111100000110)
2
10 110 001 101 011.111 100 000 110
2 6 1 5 3 . 7 4 0 6

(26153.7406)
8

Hexadecimal (2 4 = 16)


(10110001101011.111100000110)
2
10 1100 0110 1011.1111 0000 0110
2 C 6 B . F 0 6
(2C6B.F06)
16
16

Binary Numbers : Operations

Summation
101101
+100111
----------
1010100

Multiplication
1011
101
----------
1011
0000 .
1011 . .
----------
110111

Subtraction
101101
-100111
----------
000110
17

Two’s complement notation systems
18

Diminished Radix Complements

Complements are used in digital computers for simplifying the subtraction operation and for logical manipulation.

Given a number N in base r having n digits, the (r-1) ’s complement of N is defined as
(r n -1) –N

For decimal numbers, r = 10 and r-1 =9 So,

The 9’s complement of N is (10 n -1)-N = 999..99-N

For binary numbers, r=2 and r-1=1 so ,

The 1’s complement of N is (2 n -1)-N=111…111-N
19

Radix Complements

The radix complement of an n-digit number
N in base r is defined as r n -N for N≠0 and 0 for N=0. i.e. the radix complement= diminished radix complement +1
20

Complements

The complement of 012398 is

9
’ s complement (diminished radix complement)

• (999999)
10
-(012398)
10
= (987601)
10
10
’ s complement (radix complement)
• (987602)
10
= (987601)
10
+ 1=(987602)
10
• (1000000)
10
-(012398)
10
=(987602)
10 or:

The complement of 1101100 is

1
’ s complement (diminished radix complement)



(1111111)
2
- (1101100)
2
= 0010011
2
’ s complement (radix complement)
(10000000)
2
- (1101100)
2
= 0010100
21

•The
(r-1)’s complement of octal or hexadecimal numbers is obtained by subtracting each digit from
7 or F (decimal 15) respectively
22

Examples:
(1): 10’s complement of (52520)
10
= 10 5 – 52520 =47480
(2): 10’s complement of (246700)
10 is 753300
(3): 10’s complement of (0.3267)
10
= 1.0-0.3267 = 0.6733
(4): 2’s complement of (101100)
2
=(2 6 )
10
-(101100)
2
=(1000000)
2
-(101100)
2
=(010100)
2
(5): 2’s complement of (0.0110)
2
=(2 0 )
10
-(0.0110)
2
=(1-0.0110)
2
=(0.1010)
2.

Subtraction with Complement


10
2

’
’ s complement
Subtract 72532
–
3250 s complement
72532
10’s complement: +96750
---------
Sum: 169282
Remove end carry: -100000
---------
Answer: 69282

Subtract 1010100 - 1000011
1010100
2’s complement: +0111101
---------
Sum: 10010001
Remove end carry: -10000000
---------

Signed Binary Numbers 1

Due to hardware limitation of computers, we need to represent the negative values using bits . Instead of a
“
+
” and
“
-
” signs.

Conventions:

0 for positive

1 for negative
25

Signed Binary Numbers 2

(9)
10
= (0000 1001)
2

1. Signed magnitude (used in ordinary arithmetic):


(-9)
10
= (1000 1001)
2
Changing the first
“ sign bit
” to negative

2. Signed 1
’ s complement:

(-9)
10
= (1111 0110)
2

Complementing all bits including sign bit

3. Signed 2
’ s complement:


(-9)
10
= (1111 0111)
2
Taking the 2
’ s complement of the positive number
26

27

Arithmetic Addition and Subtraction
+6
+13
+19
+ 6
- 13
- 7
00000110
00001101
00010011
00000110
11110011
11111001
- 6
+13
+7
- 6
- 13
- 19
11111010
00001101
00000111
11111010
11110011
11101101
28

Binary Logic

Binary Logic: Consists of Binary Variables and
Logical Operations

Basic Logical Operations:

AND

OR

NOT

Truth tables: Table of all possible combinations of variables to show relation between values
29

Logical Operation: AND

Value
“
1
” only if all inputs are
“
1
”

Acts as electrical switches in series

Denote by
“ . ”
0
1
X
0
1
1
0
Y
0
1
X.Y
0
0
0
1
30

Logical Operation: OR

Value
“
1
” if any of the inputs is
“
1
”

Acts as electrical switches in parallel

Denote by
“
+
”
0
1
X
0
1
1
0
Y
0
1
X+Y
0
1
1
1
31

Logical Operation: NOT

Reverse the value of input

Denote by complement sign ( !x or x
’ or x ).

Also called
“ inverter
”
X
0
1
X
’
1
0
32

Logic Gates

Is electronic digital circuits (logic circuits)
[Mano p.29-30]

Is blocks of hardware Called
“ digital circuits
”
,
“ switching circuits
”
,
“ logic circuits
” or simply
“ gates
”
33

X-OR Gates
34

Input-Output Signals
35

Binary Signals Levels
2
1
0.5
0
-0.5
4
Volts
3
Logic 1

Acceptable level of deviation

Nominal level

State of transition
Logic 0
36

Positive and negative logic
37

BCD Code

Although the binary number system is the most natural system for a computer, most people are more accustomed to decimal system.

Convert decimal numbers to binary, perform all arithmetic calculations in binary and then convert the binary results back to decimal.

So, we represent the decimal digits by means of a code that contains 1
’ s and 0
’ s.

Also possible to perform the arithmetic operations directly with decimal numbers when they are stored in coded form.
38


Ex1: BCD for (396)
10 is (0011 1001 0110)
BCD

Ex2: (185)
10
=(0001 1000 0101)
BCD
= (10111001)
2

So, the BCD has 12 bits, but binary equivalent has 8 bits
39


9
4
+ 5
0100
0101
1001
4 0100 8 1000
+8 1000 +9 1001
12 1100
+ 0110
17 10001
+ 0110
1 0010
Binary Carry 1 1
1 0111
0001 1000 0100 184
+0101 0111 0110 +576
Binary sum 0111 10000 1010
Add 6 0110 0110
BCD sum 0111 0110 0000 760
40


Add (+375) + (-240)= +135
0 375
Complement of 240
+ 9 760
Discard the end carry
0 135
The 9 in the leftmost position of the second number represents a minus
41

42

Gray Code
Binary
0000
0110
0111
1000
1001
1010
0001
0010
0011
0100
0101
1011
1100
1101
1110
1111
1-bit change
…
1-bit change
Reflected Code
(Gray code)
0000
0101
0100
1100
1101
1111
0001
0011
0010
0110
0111
1110
1010
1011
1001
1000
Decimal Digit
0
8
9
6
7
10
3
4
1
2
5
11
12
13
14
15
43

ASCII Character Code

The ASCII (American Standard Code for
Information Interchange)

7 bits per character to code 128 characters including special characters ($ = 0100010)

It uses 94 graphic characters that can be printed and
34 non-printing characters used for control functions.

There are 3 types of control characters: format effectors, information separators, and communication control characters.
44

45

ASCII Control Characters
46


Although ASCII code is a 7-bitcode, ASCII characters are most often stored one per byte.

The extra bit are used for other purposes, depending on the application.

For Ex., some printers recognize 8-bit ASCII characters with the MSB set to 0.

Additional 128 8-bit characters with the MSB set to 1 are used for other symbols such as the Greek alphabet or italic type font.
47


To detect errors in data communication and processing, the eighth bit is used to indicate parity.

This parity bit is an extra bit included with a message to make the total number of 1’s either even or odd.
with even parity with odd parity

Ex:
ASCII A = 1000001 01000001 11000001
ASCII T = 1010100 11010100 01010100
48

The ASCII codes for the letters A and F adjusted for odd parity
49

Transfer of information with registers
50

Example of Binary information system
51

Exercises

Problem 1-2

Problem 1-3

Problem 1-10

Problem 1-16

My Advise :
Do all problems p: 30-31,
52

Boolean Algebra & Logic Gates
Chapter 2
53


Agenda

Basic definitions

Proprieties of Boolean
Algebra

Boolean Functions

Objectives

Understanding the canonical forms

Maxterms and minterms

Canonical and standard
Forms

Reading
• Mano: Ch 2

Simplifying Boolean expression and functions
54

Boolean Algebra

The mathematical system that operate with binary values (George Boole (1854) )

Is the algebraic structure defined on a set of elements with two binary operators + (OR) and .
(AND) provided that the following
Huntington postulates are satisfied:

Reading :
Mano Chapter 2
55

1. (a) closures w.r.t operator +
(b) closures w.r.t operator .
2. (a) An identity element w.r.t + (0): x + 0 = 0 + x = x
(b) An identity element w.r.t . (1) : x . 1 = 1 . x = x
3. (a) Commutative w.r.t +: x + y = y + x
(b) Commutative w.r.t . : x . y= y . x
4. (a) . is distributive over +: x . (y + z) = ( x . y) + ( x . z)
(b) + is distributive over .: x + (y . z) = (x + y) . (x + z)
5. The complement of x is such that (a) x + x
’
=1 and
(b) x . x
’
=0
6. There exist at least 2 elements x , y such that x ≠ y
56


Is defined on a set of 2 elements, B = {0,1} with rules for the two binary operators + and . as shown in the following tables:

These rules are exactly the same as the AND, OR, and Not operations.
0
1
1
X
0
1
0
1
Y X.Y
0 0
0
0
1
0
1
1
X
0
1
0
1
Y X+Y
0 0
1
1
1
X
0
1
X
’
1
0
57

Huntington Postulates on the Two-Valued Set and the two Binary Operators
1. closures is obvious from the tables as the result of each operation is either 0 or 1
2. (a) An identity element w.r.t + (0): 0 + 0 = 0 , 0+1 = 1+0 =1
(b) An identity element w.r.t . (1) : 1 . 1 = 1 , 1 . 0 = 0 . 1 =0
3. The Commutative laws are obvious
4. (a) the distributive law : x . (y + z) = ( x . y) + ( x . z) can be verified by the truth table of all possible values of x, y and z
(b) the distributive law: x + (y . z) = (x + y) . (x + z) can also be verified by the truth table of all possible values of x, y and z
5. The complement of x (a) x+x
’
=1: 0+0
’
= 0+1=1 and 1+1
’
= 1+0 =1
(b) x . x
’
= 0: 0.0
’
= 0.1=0 and 1.1
’
= 1.0 =0
6. The two valued Boolean algebra has two distinct elements 1 and 0 with 1
≠0
58

Truth Tables Verification x y z y + z x . ( y + z )
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1 x y z x . y x . z (x . y)+( x . z )
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 1
1 1 0 1 0
1 1 1 1 1
0
0
0
0
0
1
1
1
59

Property of Boolean Algebra 1

Closure

Obtaining a unique elements (which are the members of Boolean set)

Associative Law

(X*Y)*Z = X*(Y*Z)

(X+Y)+Z = X+(Y+Z)

Commutative Law

X*Y = Y*X

X+Y = Y+X
60

Property of Boolean Algebra 2

Identity Element

1.X=X.1=X

0+X=X+0=X

Inverse


X. X
’
=0
X+ X
’
=1

Distributive Law
X+(Y.Z)=(X+Y).(X+Z)
61

Basic Theorems

Duality

Huntington (1904) postulate that of an algebraic expression, we can simply interchange OR and AND operator and replace
1 by 0 and 0 by 1

[ We will discuss this more in future sessions when you enter the realm of digital design ]
62

Postulates and Theorems of Boolean Algebra
Postulate 2
Postulate 5
(a) x + 0=x
(a) x + x’=1
(b) x .1=x
(b) x . x’=0
Theorem 1
Theorem 2
(a) x + x=x
(a) x+1=1
(x’)’ = x
(b) x . x=x
(b) x . 0=0
Theorem 3 Involution
Postulate 3 Commutative (a) x +y=y +x
Theorem 4 Associative (a) x +(y +z)=(x +y) +z
(b) x y=y x
(b) x (y z)=(x y) z
Postulate 4 Distributive (a) x (y +z)= x y+ x z (b) x +y z=(x +y) (x +z)
Theorem 5 DeMorgan (a) (x +y)’=x’ y’ (b) (x y)’=x’ + y’
Theorem 6 Absorption (a) x + x y= x (b) X (x +y)=x
63


Theorem 1(a): x+x=x.

Proof:
 x + x = (x+x) .
1 (postulate 2b)=
= (x + x) .
(x + x') (postulate 5a
= x + xx' = x (postulate 4b)

Theorem 1(b): x .
x=x

Proof:
 x .
x = xx +0 = x x + x x' = x .
(x+x')= x . 1 = x
64


Theorem 2(a): ): x +1=1.

Proof:
 x+1= 1 . (x+1) = (x+x')(x+1) = x+x' . 1 = x+x' =1

Theorem 2(b): x .0=0.

Proof: by duality x.0=0
65


Theorem 6(a): x+xy=x.

Proof:
 x +x y=x.1+xy=x(1+y)=x (y+1)=x.1=x

Theorem 6(b): x(x+y)=x.

Proof: By duality x y x y x + x y
0 0 0
0 1 0
1 0 0
1 1 1
0
0
1
1
66

(a) (x + y)
’
= x
’ y
’
x y)
’
=x
’
+ y
’ x
1
1
0
0 1
0
1
0 y x + y
(x + y)
’
0 1
1
1
1
0
0
0 x
’ y
’ x
’ y
’
1
1
0
0
1
0
1
0
1
0
0
0
67

Operator precedence

Parenthesis

NOT

AND

OR
68

Boolean Functions 1

F
1
=x+y
’
.z

F
2
=x.y.z
’
0
0
0
X
0
1
1
1
1
0
1
1
Y
0
1
1
0
0
1
0
1
Z
0
0
1
0
1
0
0
0
0
1
0
F
2
0
0
1
1
0
0
1
1
F
1
0
1
69

Boolean Functions 2
HW : give the truth table of Functions F1 and F2
70

Algebraic Manipulation

Simplify the following Boolean function to a minimum number of literals:
(1) F (x , y) = x (x' + y)
(2) F (x , y) = x + x' y
(3) F (x , y) = (x + y) (x + y')
(4) F ( x , y , z) = x y + x' z + y z
(5) F( x, y, z) = (x + y) (x' + z) (y + z)

Solution:
(1) F (x , y) = x x' + x y = 0 + x y = x y
(2) F (x , y) = (x + x') ( x + y) = 1.(x + y) = x + y
(3) F (x , y) = x + y y' = x + 0 = x or
= x + x y' + y x + y y' = x (1 + y' + y)= x . 1 = x
(4) F (x , y , z) = x y + x' z + y z (x + x' ) = x y + x' z + x y z + x' y z
= x y (1 + z) + x' z (1 + y) = x y + x' z
(5) (x + y) (x' + z) (y + z)=(x + y) (x' + z) by duality from 4
71

Complement of a Function

De Morgan

(X+Y)
’
= X
’
.Y
’

(A+B+C)
’





= (A+X)
’ with X=B+C
= A
’
X
’
(De Morgan)
= A
’
.(B+C)
’
= A
’
.(B
’
C
’
)
= A
’
.B
’
.C
’
(De Morgan)
(Associative)
72

Complement of a Function

Example:
Find the complement of the functions:
(1) F=A+B+C.
(2) F1=x' y z' + x' y' z
(3) F2= x (y' z' +y z)

Solution:
(1) F'=(A+B+C)'=A'B'C '
(2)F1'=(x' y z' + x' y' z)' = (x' y z')' (x' y' z)'
= (x + y' + z) (x + y + z')
(3) F2'=x' + (y + z) (y' + z')
73

Canonical Forms

Binary Variable can either be:


Normal Form (x)
Complement Form (x
’
)

For 3 binary variables (x, y, z) there are 8 possibility of response for AND operation
(minterms) and 8 possibility of OR operation
(maxterms)
74

Minterms #1
 “ Minterms ” or “ Standard Product ”

2 Binary Variable (X & Y) will form 2 n=2
Minterms

X
’
Y
’
, X
’
Y, XY
’
, XY

AND Terms ( “ product ” )

Any Boolean function can be expressed as a sum of Minterms
75

Minterms and Maxterms for three binary variables: x
1
1
1
0
0
0
0
1
Z
1
0
1
0
1
0
1
0 y
0
1
1
1
1
0
0
0
Minterms Maxterm
Term Designation Term Designation x'y'z' x'y'z x'yz' x'yz xy'z' xy'z xyz' xyz m
5 m
6 m
7 m
0 m
1 m
2 m
3 m
4 x+y+z x+y+z' x+y'+z x+y'+z' x'+y+z x'+y+z' x'+y'+z x'+y'+z'
M
5
M
6
M
7
M
0
M
1
M
2
M
3
M
4
76

Function of three variables x y Z Function f1 Function f2
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
0
1
0
1
0
0
F1=x’ y’ z + x y’ z’ + x y z = m1+m4+m7
F2= x’ y z + x y’ z + x y z’ + x y z = m3 + m5 + m6 + m7
F
’
+y
1
= x’ y’ z’ + x’ y z’ + x’ y z + x y’ z + x y z’
The complement of F’
’ +z)
1
=(x+y+z)(x+y’+z )(x+y’+z’)( x’+y+z’) (x ’
77
=F
1
= M
0
.M
2
.M
3
.M
5
.M
6

Minterms #2

Example 2-4








(page 46)
F = A + B
’
C
F = A (B + B
’
) + B
’
C
F = AB + AB
’
+ B
’
C
Sum of Minterms
F = AB (C + C
’
) + AB
’
(C + C
’
) + B
’
C
F = ABC + ABC
’
+ AB
’
C + AB
’
C
’
+ B
’
C
F = ABC + ABC
’
+ AB
’
C + AB
’
C
’
+ (A + A
’
) B
’
C
F = ABC + ABC
’
+ AB
’
C + AB
’
C
’
+ AB
’
C + A
’
B
’
C
F = ABC + ABC
’
+ AB
’
C + AB
’
C
’
+ A
’
B
’
C

F = m7 + m6 + m5 + m4 + m1
(Table 2-5, page 47)

F(A, B, C) = ∑(1, 4, 5, 6, 7)
78

F=A+B
C
A
1
1
1
1
0
0
0
0
B
1
1
0
0
1
1
0
0
C
0
1
0
1
0
1
0
1
F
1
1
1
1
0
0
0
1
79

Maxterms
 “ Maxterms ” or “ Standard Sums ”

2 Binary Variables (X & Y) will form 2 n=2
Maxterms

X
’
+Y
’
, X
’
+Y, X+Y
’
, X+Y

OR Terms ( “ sum ” )

Any Boolean function can be expressed as a product of Maxterms

F2=(x+y+z)(x+y+z
’
)(x+y
’
+z)(x
’
+y+z)

F2=M
0 .
M
1 .
M
2 .
M
4
=Π(0,1,2,4)
80

Minterms & Maxterms #1

Minterms

X
’
Y
’
, X
’
Y, XY
’
, XY

Maxterms

X
’
+Y
’
, X
’
+Y, X+Y
’
, X+Y

Each Maxterms is the complement of its corresponding Minterms & vice versa

Remember De Morgan ?

Take a look at the next slide
81

Minterms & Maxterms #2 x y z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Term x
’ y
’ z
’ x
’ y
’ z x
’ y z
’ x
’ y z x y
’ z
’ x y
’ z x y z
’ x y z
Minterms
Desig.
m
4 m
5 m
6 m
7 m
0 m
1 m
2 m
3
Maxterms
Term x + y + z x + y + z
’ x + y
’
+ z x + y
’
+ z
’ x
’
+ y + z x
’
+ y + z
’ x
’
+ y
’
+ z x
’
+ y
’
+ z
’
Desig.
M
4
M
5
M
6
M
7
82
M
0
M
1
M
2
M
3

Conversion between canonical forms
F=xy + x’z
The function F expressed in sum of minterms is:
F(x,y,z)= ∑(1,3,6,7)
The missing terms are 0,2,4,5
Then, The function F expressed in product of maxterm is:
F(x,y,z)= Π(0,2,4,5)
X Y Z F
1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
83

Standard Forms

Doesn ’ t have to consists of all variables


Sum of Products : F
1
Products of Sum : F
2
= y
’
+ xy + x
’ yz
’
= x (y
’
+ z) (x
’
+ y + z
’
)
84

Implementation with two and three levels
85

Truth table for 16 functions of 2 binary variables
X Y F
0
F
1
F
2
F
3
F
4
F
5
F
6
F
7
F
8
F
9
F
1
0
F
11
F
12
F
13
F
14
F
1
5
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
86

Other Logic Operations
Operator Symbol Boolean Operator
F0 = 0
F1 = xy
F2 = xy
’
F3 = x
F4 = x
’ y
F5 = y
F6 = xy
’
+ x
’ y
F7 = x + y
F8 = (x + y)
’
F9 = xy + x
’ y
’
F10 = y
’
F11 = x + y
’
F12 = x
’
F13 = x
’
+ y
F14 = (xy)
’
F15 = 1 x.y
x/y y/x x
 y x+y x
 y
(x
 y)
’ y
’
X
 y x
’
X
 y x
 y
Name
Null
AND
Inhibition
Transfer
Inhibition
Transfer
Exclusive OR
OR
NOR
Equivalence
Complement
Implication
Complement
Implication
NAND
Identity
Comments
Binary Constant 0 x and y x but not y x y but not x y x or y but not both x or y
Not OR x equals y
Not y
If y then x
Not x
If x then y
Not AND

Common Logic Gates








AND
OR
Inverter
Buffer
NAND
NOR
XOR
XNOR
Figure 2-5 (page 54)
88

Positive and negative logic
89

H
Positive and negative logic ( Contd .)
90


Levels of Integration
1- Small-Scale Integration (SSI)
Number of gates are < 10
2- Medium-Scale Integration (MSI)
Number of gates are from 10 to 1000
3- Large-Scale Integration (LSI) contains thousands of gates in a single package
4- Very Large-Scale Integration (VLSI) contains hundred of thousands of gates in a single package
91


Digital ICs are classified not only by their complexity or logical operations but also by the specific circuit technology to which they belong which is referred to as digital logic family.

The basic circuits in each technology is a
NAND, NOR, or inverter gate.

The electronic components employed in the construction of the basic circuit are usually used to name the technology.
92

Contd

The most popular logic families are:
1TTL Transistor-Transistor Logic is being in operation for a long time and is a standard
2ECL Emitter-Coupled Logic has an advantages in systems requiring high speed operation
3MOS Metal-oxide Semiconductor suitable for circuits that need high component density
4CMOS Complementary Metal-oxide Semiconductor preferable in systems requiring low power consumption as in VLSI
93

Digital Logic families parameters

These are the parameters that are evaluated and compared for different families:
1Fan-out: the number of standard loads that the output of a gate can drive.
2Fan-in: the number of inputs available in the gate.
3Power dissipation : power consumed by the gate that must be available from the power supply.
4Propagation delay: average transition delay time for the signal to propagate from input to output.
5Noise margin: is the maximum external noise voltage added to an input signal that does not cause an undesirable change in the circuit output
94

Computer-Aided Design (CAD)

Software programs that support computerbased representation and aid in the development of digital hardware by automating the design process.
95

Exercises

HW :
Problems 2-1 until 2-23 Mano
96

Gate Level Minimization
 Chapter 3
97


Agenda


Simplification of
Boolean Functions
(The K-Map Method)
Don’t Care Condition

Synthesis with NAND
& NOR Gate

Brief on Gate
Implementation

Objectives



Understand the procedure of simplifying Boolean functions
Understand and able to perform the K-Map method
Understand the Don’t Care
Condition and their place in
K-Map Method

Main Reading
• Mano: Ch 3

Understand and able to implement design in NAND and NOR Gate

Understand the basic of Gate
Implementation
98

The Map Method

Provides a simple straightforward procedure for minimizing Boolean functions

Proposed by Veitch (Veitch Diagram), modified by Karnaugh (Karnaugh Map)

Why bother?
• Simplifying the function = minimizing the amount of gates
• Industrial requirements for efficiency in mass production
99

2-Variable Map

The Map represents a visual diagram of all possible ways a function may be expressed in a standard form
100

2-Variable Map
Representing Function in the map
• F= x.y

F= x+y = x
’ y + xy
’
+ xy
101

3-Variable Map

The Map represents a visual diagram of all possible ways a function may be expressed in a standard form
102

3-Variable Map : Example F(x,y,z)
103

3-Variable Map rules of combination

One square represents one minterm, giving a term of 3 literals.

Two adjacent squares represent a term of 2 literals

Four adjacent squares represent a term of 1 literal.

Eight adjacent squares encompass the entire map and produce a function that always equal to 1.
104

3-Variable Map :
Other Examples F(x,y,z)
105

3-Variable Map :
Other Examples F(x,y,z)
106

Simplifying using the Map

F = A
’
C + A
’
B + AB
’
C + BC

Plot the expression

Find minimum adjacent squares
• Prime Implicant
• Essential Prime Implicant

Draw them

Write the expression
A
A
BC
00
0
1
01
1
11
1
B
10
1
1
C
1
F = C + A’B
107

4-Variable Map
108

4-Variable Map rules of combination

One square represents one minterm , giving a term of 4 literals.

Two adjacent squares represent a term of 3 literals.

Four adjacent squares represent a term of 2 literals.

Eight adjacent squares represent a term of 1 literal.

Sixteen adjacent squares represent the function equal to 1.
109

4-Variable Maps (Example)

F(w,x,y,z) =
∑(0,1,2,4,5,6,8,9,

12,13,14)

0000, 0001, 0010,
0100, 0101, 0110,
1000, 1001, 1100,
1101, 1110
 f(w,x,y,z)=y’+w’z’+xz’
110

4-Variable Maps (Example)

Simplify the
Boolean Function:
F= A’B’C’ + B’CD’ +
A’BCD’ + AB’C’
Solution:
The simplified function is:
F=B’D’ + B’C’ + A’ CD’
111

5-Variable Map
112

5-variable Map
F(w,x,y,z) = ∑(0,2,4,6,9,13, 21, 23, 25, 29,31)
113

Product of Sum Simplification

F(w,x,y,z) =
∑(0,1,2,4,5,6,8,9,

12,13,14)

0000, 0001, 0010,
0100, 0101, 0110,
1000, 1001, 1100,
1101, 1110 w wx yz
00
00 1
01
11
1
1
10 1
1
1
01
1
1
0
0
11
0
0 y
1
1
10
1
0 z x
114

Product of Sum Simplification

F(w,x,y,z) =
∑(0,1,2,4,5,6,8,9,

12,13,14)

0000, 0001, 0010,
0100, 0101, 0110,
1000, 1001, 1100,
1101, 1110
 f(w,x,y,z)=y’+w’z’+xz’
115

Product of Sum Simplification
F' = yz+wx’y
F=(F’)’
F=(yz + wx’y)’
F=(yz)’(wx’y)’
F=(y’+z’)(w’+x+y’) wx yz
00
00 1
01 w
11
10
1
1
1
1
1
01
1
1 z
0
0
11
0
0 y
1
1
10
1
0 x
116

Are they the Same?

F = y' + w'z' + xz'

F'= yz + wx'y




(F
’
)
’
(yz + wx
’ y)
’
(yz)
’
(wx
’ y)
’
(y
’
+z
’
)(w
’
+x+y
’
)


Normal Simplification (Sum of Product)
Product of Sum Simplification y'w' + y'x + y'y' + z'w' + z'x + z'y' y'(w' + x + z' + y') + z'w' + z'x
 y'+ z'w' + z'x
117

Product of sums simplification
118

Gates Implementation : example
119

Don’t Care Conditions :

Sometimes a certain combination of inputs will never be evaluated by your digital system, thus a
“Don’t care” is placed for those valuation

E.g. consider a BCD ( Binary Coded Decimal ) number, there are 4 binary variables b
3
,b
2
,b
1
,b
0 that represents decimal 0 to 9. design a system that detect if the
BCD input given is divisible with 3
• 4 bits has 16 combinations, but only 10 are used to represent decimal 0 to 9, the remaining combinations are not used.
• System will produce 1 if the BCD is divisible by 3.
120

Don’t Care Example b
3 b b
2
1 b
0
00
00 0
01
11
10 0
0 d
0 d
01
0
1
0 d
11
1 d
1 d
10
0 d
Decimal Binary
Represe ntation b
3 b
2 b
1 b
0
0
1
2
0
0
0 f
0 0 0 0
0 0 1 0
0 1 0 0
5
6
3
4
7
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
8
9
1 0 0 0 0
1 0 0 1 1
Unused 1 0 1 0 d
Unused 1 0 1 1 d
Unused 1 1 0 0 d
Unused 1 1 0 1 d
Unused 1 1 1 0 d unused 1 1 1 1 d

Simplifying With Don’t Cares b
2 b
1 b
0
’+b
2
’b
1 b
0
+b
3 b
0
You can either use or not use the don’t care cell
(it can be treated like a “1” if it can produce more efficient result) b
3 b
2 b
1 b
0
00
00 0
01 0
01
0
0
11
1
0
10
0
1
11 d d d d
10 0 1 d d
122

So What Does Don’t Care Means?

We simply don’t care what the function values are for the unused input valuation
Denote by “ d
” or “ x
”

Keep in mind to use as minimum amount of terms as possible
123

Example with don’t Care condition
Simplify :
F(W,X,Y,Z)=
∑(1,3,7,11,15)
With the Don’t care conditions of: d(w,x,y,z)=
∑(0,2,5)
F(w,x,y,z)= yz+w'x'= ∑(0,1,2,3,7,11,15)
F(w,x,y,z)= yz+w'z= ∑(1,3,5,7,11,15)
F ' =z'+wy‘
F(w,x,y,z) = z(w'+y)=
∑(0,2,4,6,8,9,10,12,13,14)
124

Implementation of Logic Gates

Inverter

NOR

NAND

In the market, logic gates are more commonly implemented using NAND and NOR gates rather than AND & OR

Because It is easier to manufactured
125

NOT, AND & OR Gates implementation using NAND x x y x y
X'
NOT xy
AND
(x’y’)’ = x+y
OR
126

NAND Gate’s Symbols

NAND Gate as Universal Gate

Any gate can be represented using NAND

Implemented as if AND-Invert or Invert-OR

(xyz)' = x' + y' + z'
=
127

Two-Level Implementation
F=[(AB)
''
+(CD)
''
] =AB+CD

F = AB + CD
A
A
B
B
F
C
C
D
D
A
B
F=[(AB)
‘.
(CD)
'
]
'
= [(A+B) . (C+D)]
‘
= AB+CD
C
D
128
F
F

Two-Level Implementation

F = AB + CD
A
B
C
D
Read the summary of procedure in
Page 85 (top)
Level-2
F
C
D
A
B
B
C
D
F
129
F

Example
Implement the following Boolean function with NAND gates:
F(x,y,z) = (1,2,3,4,5,7)
130

Implementation with NAND gates procedure :
1- Simplify the function and express it in sum of products.
2- Draw a NAND gate for each product term of the expression that has at least two literals.
3- Draw a single gate using the AND-invert or the invert-OR in the second level.
4- A term with a single literal requires an inverter in the first level. However, if the single literal is complemented, it can be connected directly to an input of the second level NAND gate
131

Multilevel Logic Circuit #1

To obtain a multilevel NAND diagram from a Boolean Expression:

Draw the Logic Diagram

F = A (CD + B)+BC'
‘
132

Multilevel Logic Circuit # 2
 Convert all AND gates to NAND gates with AND invert graphic symbol
 Convert all OR gates to NAND gates with Invert OR graphic symbol.

Check all the bubbles in the diagram. For every bubble that is not compensated by an other small circle along the same line, insert an inverter (one input NAND gate) or complement the input literal.
‘
133

•Consider the multilevel Boolean function:
F = (AB ' + A ' B)(C+D ' )
134

NOR Implementation

Universal Gate : The NOR gate is said to be a universal gate because any digital system can be implemented with it.
135

NOR Gate Symbol

Implemented as if OR-Invert or Invert-AND

(x' y' z') = (x + y + z)'
136


Implement the following Boolean function with NOR gates:
F = (A+B)(C+D)E
137

Multilevel Logic Circuit with NOR Implementation
•Give the NOR multilevel implementation for the Boolean function:
F = (AB ' + A ' B)(C+D ' )
138

Exclusive OR Function x  y = xy‘ + x'y
XNOR: Inverted XOR
(x  y)’ = xy + x’y’
X Y
X

Y
1
1
0
0
0
1
0
1
0
1
1
0 x  0 = x x  1 = x' x  x = 0 x  x' = 1 x  y' = x'  y=(x  y)'
139

Exclusive OR Implementation
The first NAND gate perform the operation (xy) ' = (x ' +y ' )
Then x  y= (x ' +y ' )x+(x ' +y ' )y
= xy ‘ + x'y= x  y
140

Odd Function
A  B  C= (AB ' +A ' B)C ' + (AB +A ' B ' )C
=AB ' C ' +A ' BC ' +ABC+A ' B ' C
= ∑(1,2,4,7)
This means that in the 3 or more variable case the requirement of XOR function to be equal to 1 is that an odd number of variables be equal to 1
141

Three Variable XOR Odd and Even Function
142

Four Variable XOR Odd and Even Functions
A  B  C  D= (AB ' +A ' B)  ( CD ' + C ' D)
=(AB ' +A ' B)(CD+C ' D ' ) + (AB +A ' B ' )(CD ' +C ' D)
= ∑(1,2,4,7,8,11,13,14)
C
C
AB
CD
00 01 11 10
AB
CD
00
00
01
1
11 10
1
00 1 1
01 1 1
01 1 1
B
A
11
10 1
1
1
1
A
11
10
1
1
1
1
B
D
Odd Function
F = A

B

C

D
D
Even Function
F =( A

B

C

D)
'
143

x
1
1
1
1
0
0
0
0
Parity Generation and Checking
Three-Bit Message Parity Bit y
1
1
0
0
0
0
1
1
Z
0
1
0
1
0
1
0
1
P
0
1
1
0
0
1
1
0
Even Parity Generator
Truth Table
Four-Bits Received
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1 x
0
1
0
1
1
0
1
0
0
0
1
1
0
0
1
1 y
0
Z
0
P
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
Parity Error
Check
C
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
144
Even Parity checker Truth Table

Logic Diagram of Parity Generator and
Checker
145

Combinational Logic
Chapter 4
146


Agenda

Combinational Logic

Design Procedure


Adders, Subtractors
Analysis Procedure

Multilevel Logic Circuit

Reading

Mano: Ch 4

Project #1

Objectives:

Understand the nature of Combinational Logic

Understand and able to execute the combinational logic
 design procedure
147

Combinational Logic : Definition

Combinational Logic is a logical circuit consists of logic gates whose outputs at any time are determined directly from the present combination of inputs without regard to previous inputs
A
Combinational Circuit
B
148

F2=AB+AC+BC
T1=A+B+C
T2=ABC and
T3=F2' T1
F1=T3+T2
Therefore,
F1=T3+T2= F2' T1 + ABC
=( AB+AC+BC)'(A+B+C)
+ ABC
=(A'+B')(A'+C')(B'+C')(A
+B+C)+ABC
=
=A'BC'+A'B'C+AB'C'+ABC
149

1. Define the problem
2. Define the input/output variables
3. Truth table of the relationships
4. Simplify Boolean functions
5. Draw the logic diagram
Constraints:
1. Min No. of gates
2. Minimum number of inputs to a gate
3. Min Propagation time
4. Min no. of interconnections
150

Example : Code Conversion
(BCD to Excess-3)
Input BCD
A B C D
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Output Excess-3 w x y z
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
151

Example : Code Conversion
(BCD to Excess-3)
Z=D’ y=CD+C’D’=CD+(C+D)’
X=B’C+B’D+BC’D’=B’(C+D)+BC’D’
=B’(C+D)+B(C+D)’
W=A+BC+BD=A+B(C+D) 152

Common Combinational Logic
Binary Adders

Half-Adders

Full-Adders
Binary Substractors

Half-Substractors

Full-Substractors

Decoders/Encoders

Multiplexers
153

Binary Adders

One of the basic arithmetic process in computer system

One that performs the addition of 2 bits is
Half–Adder

One that performs the addition in 3 bits
(2 significant bits and a previous carry) is called Full–Adder
154

Half-Adder
2 Input & 2 output

The truth table

Thus the Boolean
Function is

S = x'y+xy';

C = xy

The function cannot be further simplified
0
1
X
0
1
Truth Table
1
0
Y
0
1
0
0
C
0
1
1
1
S
0
0
155

Half-Adder Implementations
156

Full–Adder Truth Table

3 Input (x & y as the input and z as the previous carry), & 2 output (s, c)

The truth table is :
1
1
0
1
1
0
0
X
0
0
1
1
0
1
0
1
Y
0
1
0
1
0
1
1
0
Z
0
1
1
1
0
1
0
0
C
0
0
0
0
1
1
1
1
S
0
157

Full-Adder Map
158

Full–Adder Simple Implementation

Logic Expression
S = x'y'z+x'yz'+xy'z'+xyz
C = xy + xz + yz

Implementation
159

Full–Adder Implementation
S=z  (x  y)
=z’ (xy’ + x’y) +z(xy’ + x’y)’
= z’(xy’ + x’y) + z(xy + x’y’)
= xy’z’ + x’yz’ + xyz + x’y’z
C=z (xy’ + x’y) + xy
=xy’z + x’yz + xy
160

Full–Adder Application
161

Example:
A=1011, B=0011 then S= 1110
Subscript i
Input carry
Augend
Addend
Sum 1
Output carry 0
3
0
1
0
2
1
0
0
1
0
1
1
1
1
1
1
0
0
1
1
0
1
C i
A i
B i
S i
C i+1
162

Full–Adder Other Implementation
P i
=A
G i i
 B i
= A i
B i
S i
C i+1
=P
= G i i
 C i
+ P i
C i
G i
: Carry generate
P i
: Carry propagate
163


The total propagation time is equal to the propagation delay of a typical gate times the number of gate levels in the circuit.
C
0
=input carry
C
1
= G
0
+P
0
C
0
C
2
=G
1
+P
1
C
1
=G
1
+P
1
(G
0
+P
0
C
0
)=G
1
+P
1
G
0
+P
1
P
0
C
0
C
3
=G
2
+P
2
C
2
=G
2
+P
2
G
1
+P
2
P
1
G
0
+P
2
P
1
P
0
C
0
164

C
0
=input carry
C
1
= G
0
+P
0
C
0
C
2
=G
1
+P
1
C
1
=G
1
+P
1
(G
0
+P
0
C
0
)=G
1
+P
1
G
0
+P
1
P
0
C
0
C
3
=G
2
+P
2
C
2
=G
2
+P
2
G
1
+P
2
P
1
G
0
+P
2
P
1
P
0
C
0
165

Adder with carry lockahead Genertaor
166


One of the basic arithmetic process in computer system

One that subtracts 2 and produce their difference is Half-Substractor

One that subtracts 2 and produce their difference while taking account that 1 have been borrowed by a lower significant stage.
 it is called : Full-Substractor
167

Half-Substractor

2 Input & 2 output
(Borrow & Data)

Boolean Function cannot be simplified

D = x'y + xy'

B = x'y
0
1
X
0
1
Truth table
1
0
Y
0
1
1
0
B
0
0
1
1
D
0
0
168

Full-Substractor

You do it

Truth table

Simplify with K-Map

Draw the Logic Gate
169

Adder-Substractor

The operation A-B =A+ “1’s complement of B” +1
= A+ “2’s complement of B.

For unsigned numbers, this gives A-B if A>= B or the 2’s complement of (B-A) if A < B.

For signed numbers the result is A-B provided that there is no overflow.

The addition and subtraction operations can be combined into one circuit with one common binary adder and including an X-OR gate with each full adder.
170

Adder-Substractor
When M=0, the circuit is adder
(since B

0 = B), and when M=1, the circuit is subtractor (since B

1 = B' ).
171

Carries: 0 1
+70 0 1000110 carries:1 0
-70 1 0111010
+80 0 1010000
+150
-80 1 0110000
1 0010110 -150 0 1101010
172

Binary Multiplier
173

4 by 3 Binary Multiplier
C3 C2 C1 C0
C4 C3 C2 C1
C5 C4 C3 C2
C5 C4 C3 C2
174

Decoder
Inputs Outputs x y z D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
175

2-4 Line Decoder (1-4 line Demultiplexer)
176

Chapter 5


Agenda

Synchronous
Sequential Logic
• Flip-flops rev

Reading

Mano: Ch 5
(pp.167-178)

Understand what
Synchronous
Sequential Logic is and how it differs to
Combinational Logic

Understand the Flip-
Flops as basic
Synchronous
Sequential Logic
178


Agenda

More Combinational
Logic Circuit

Synchronous Sequential
Logic
• Design Procedures

Reading

Mano: Ch 4

Mano: Ch 5

Activities

Understand a more complex Combinational
Circuits

Understand the design procedure of Sequential
Logic Circuits

Exercise #4

Simulation Tools Demo
179

Sequential Logic
In practice there is a lot of digital system that requires memory elements


Where the next sequence of output depends on the previous output.
Since more than one parts exist, we need to synchronize them.
Inputs
Combinational
Circuit
Memory
Elements
Outputs
A
Non-combinational Circuit
B
180

Flip-flops
The Memory

The memory elements used in Clocked
Sequential Circuits are called Flip-Flops

A Flip-Flops is a Binary Cells capable of storing one bit of information
181

RS Flip-flop / RS Latch

Is the basic Flip-Flop circuit

S = Set, R = Reset

Also called direct-coupled RS flip-flop or
SR latch S
0
R
0
Q
NC
Q
’
NC
No Change
R (reset)
1 Q
1 0 1 0
S (set)
2 Q'
0
0
0
1
0
1
0
1
1
0
0
0
0 (after S=1, R=0)
1
1 (after S=0, R=1)
0
Race Condition
182

RS Flip-flop/RS Latch Timing Diagram
S R Q Q
’
0 0 NC NC
0 1 0 1
1 0 1 0
1 1 0 0
Race
R (reset)
S (set)
1
2 Q'
Q
R
S
Q
Q'
?
?
183
Time

RS Flip-flop Implementations
R (reset)
S (set)
S (set)
R (reset)
1
2
1
2
Q
Q'
Q
Q'
0
0
0
1
S
0
1
S
1
1
0
1
0
1
0
1
0
1
R
0
0
R
0
1
1
1
0
1
1
0
0
0
Q
NC
1
Q
0
0
1
1
1
NC
Q
’
NC
No Change
0
0 (after S=1, R=0)
1
1 (after S=0, R=1)
0 Race
Q
’
1
1 (after S=1, R=0)
0
0
(after S=0, R=1)
1 Race
NC

Synchronization

Synchronization is achieved using a timing device called Master-Clock Generator, which generates a periodic train of Clock
Pulses
Period

This clock is used to trigger the components.
0 1 0 1 0 1 0
Pulse Width
185

Clock Pulse Triggers
 Positive Pulse
Transition/Edge
1
0 1 0
0
 Negative Pulse
Transition/Edge
Negative Edge

Positive
Level
1 0 1
Positive Edge
186

Clocked Flip-flops

Synchronous sequential circuits that use clock pulses in the inputs of memory elements are called Clocked Sequential
Circuits

Clocked Flip-Flop is the memory part of the
Sequential Circuit which is driven by a clock pulse
187

Clocked RS Flip-flop #1

Clock Pulse (CP) as an enable signal for the other two inputs

If CP goes to 1, information from the S or R input is allowed to reach output
S
3
1 Q
CP
2 Q'
4
R
188

CP
S
R
Clocked RS Flip-flop #2
3
4
S
S E T
Q
1
2
Q
Q'
1
1
C
0
1
1
1
1
0
0
S R
X X
0
1
0
1
Q
(t+1)
No Change
No Change
0 (Reset)
1 (Set)
Intermediate/
Not Stable/
Race
R
C L R
Q
189

Indeterminate Condition
Problem in RS Flip-Flop

The indeterminate condition

(CP=1, R=1, S=1)

This place gate 3 & 4 to 0 and place 1 in both Q and Q
’

When CP goes back to 0, it is not possible to determine the next state
S

It become a 3
1 race between
Gate 3 & 4
’ s responses
CP
2

Should be
R
4 avoided
190
Q
Q'

D Flip-flops (Gated D Latch)

Eliminates the indeterminate state in
RS Flip-Flop, by ensuring R & S will never have same value
C D Q
(t+1)
0 X No Change
1 0 0 (Reset)
1 1 1 (Set)
D
S E T
Q
C L R
Q
D
CP
3
1
2
Q
Q'
4
5
191

JK Flip-flops #1
1
1
1
0
1
0
0
0

Is the refinement of RS flip-flop

J is Set, K is Reset
Q

If both is 1, the output toggles
J K Q
(t+1)
0 0 0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
1
0
1
K
CP
J
Q
JK J
00 01 11 10
0
Q 1 1
Q
(t+1)
K
=JQ’+K’Q
1 1
1
192
Q'
Q

JK Flip-flops #2

Because of the feedback connection, a CP pulse that remains in the 1 state while both J & K equals to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0


Thus the CP has to have a time duration shorter than the propagation delay time of the flip-flop
This restriction is eliminated in Master-Slave or edgetriggered Flip-flop
193

T Flip-flops

The T flip-flop works on the same principals with JK flip-flop

But instead of having 2 inputs, it has only one that will cause the Q to toggles between normal and complement form
0
1
Q T
0 0
1 1
1
0
Q
(t+1)
0
1
1
0
T
CP
194
Q'
Q

y
Q
CP
S
Master-Slave Flip-flops #1

Constructed from 2 separate flip-flops, the master and slave

The Master and Slave never enabled at the same time due to inverted clock
S
R
CP
Master
SET
S Q y
S
Slave
SET Q
R
CLR
Q y '
R
CLR
Q
195
Q
Q'

Master-Slave Flip-flops #2


Thus, any input changes during the first clock cycle will effect the master, but not the slave
Then the result of the master will determine the output of the slave on the next clock
• And during that clock, any input changes to the master will not effect the slave (because the master is already disabled again)
S
Master
S
SET Q y
S
Slave
SET Q
Q
R
R
CLR
Q y '
R
CLR
Q
Q'
CP
196

Edge-Triggered Flip-flops

D-type positive-edge-triggered flip-flop

The edge of transition
1 triggers the output change Certain
S threshold level 2
CP
3
R
5
6
4
D
Q
Q'
197

Exercise 4

Problem 5-1

Problem 5-3
198

Adders & Multiplexers

This is your project
 read the books and figure it out your self, we will talk about it later when you present your work.

199

Magnitude Comparator #1

Compares weather one number is bigger, smaller or same magnitude with the other.

A = A
3
A
2
A
1
A
0

B = B
3
B
2
B
1
B
0

Same if bits on the same position are the same

To determine greater/less we need to compare the relative magnitudes of pairs starting from the most significant bit
200

Magnitude Comparator #2 (A=B)
X3
A1
B1
A0
B0
A2
B2
X1
A= 1 1 1
B= 1 1 1
X0
A= 0 0 0
B= 0 0 0
A=B
201

A2
B2
A1
B1
A0
B0
Magnitude Comparator #3 (A>B)
X3
A= 1 1 1
B= 1 0 1
X1
X0
A>B
202

Magnitude Comparator #4 (A<B)
A= 1 0 1
B= 1 1 1
A2 X3
B2
X1 A1
B1
A0
B0
A<B
X0
A=B
203

Magnitude Comparator #5 (combined)
A2
B2
A1
B1
A0
B0
X1
X3
X0
A<B
A>B
A=B
204

Decoders #1

Decodes/convert information from one format into another format

Usually if the input is n-bits, the output is no greater than 2 n -bits

Example:
• Binary to BCD decoders
• BCD to excess-3 decoders
• Binary to 7 segment decoders
• …
. MORE
…
.
205

Decoders: Binary-to-7 Segment #1

Display the decimal digits in a recognizable format to us

Each segment is a LED (Light Emitting Diodes) that can either be On (1) or Off (0) a f g e d b c
On Off
206

Decoders Binary-to-7 Segment #2 a f g e d b c
Off
1
1
0
On
Binary decoders
7-Segments 1
1
1
1
1
1
0
207

Encoders

Encoders perform the opposite of Decoders and usually work in pairs

Perform the opposite operation of decoders

Have more input lines than output lines
3 x 7
Decoder
7 x 3
Encoder
208

Multiplexers #1

Abbreviated as MUX

Selects binary information from one of many input lines and directs it into a single output line

The selection of 2 n lines is controlled by selection n-lines inputs
209

Multiplexers #2
I
0
I
1
I
2
I
3 s
1 s
0
Y
210

Analysis of Clocked Sequential Circuits

State Table

State Diagram x y CLK
D
SET
Q
CLR
Q
A
211

Let’s do it again !!! We want to analyze this
Implementation Diagram x
D
S E T
Q
C L R
Q
A
A'
D
S E T
Q
C L R
Q
B
B'
CP y
Fig 5-15 (p.181)
212

Anatomy of a State Diagram

State is represented by a circle containing the state’s binary

The transition is represented by the directed lines
1/0

The label “1/0” means that with the input 1 the state
0/0 will change to the other state (following the arrow) and the output produced is 0
00
01
0/1
1/0
0/1
0/1
10
11
1/0
1/0
213

1/0
State Table : Drawing the State
Diagram from State Table
Current in Next
0/0
00
01
0/1
1/0
0/1
0/1
10
11
1/0
1/0 out
A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 214 0

Further Readings

In the explanation given we use D FF

Your book have example when using JK FF and T FF (read pp.185
–
189)
215

Demo

Electronic Workbench

Version 5.12

Interactive Image Technologies Ltd

You can use other simulation application, but this is one of the best I ever used

Intended for simulating the digital circuit

NOT intended to produce the wiring diagram
216