ES210, Digital Design Lab
Reporter Name:
Date:
Partner Names
Group No.:
Lab 5: Encoder and Decoder (Solutions)
A. Objectives
1. Learn how NAND gate can substitute AND, OR, NOT, and NOR gates
2. Examine Decimal to Binary Encoder.
3. Examine Binary to Decimal Decoder.
B. Introduction
The NAND gate is one of the fundamental gates and can generate all other gates including AND, OR, NOT, NOR, XOR,
and XNOR. It is also interesting to examine a simple encoder and a decoder.
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A decimal-to-binary encoder converts a decimal number that we key into a calculator or a computer to binary for the
processor to manipulate.
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A decoder coverts the output binary number of a calculator or computer to display as decimal for human readability.
C. Parts needed
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A Digital Multimeter
A +5 V power supply
A breadboard
Wires
One 7404 (NOT gate)
Three 74LS11 (triple 3-input AND gate)
Two 74LS20 (dual 4-input NAND gate)
Datasheets of the gates from the Internet.
D. Procedure
1. Generation of gates by 2-input NAND gate: Show how you can generate NOT, 2-input AND, and 2-input OR gates
using 2-input NAND gates. Draw the circuit and verify the operation.
NOT
AND
OR
NOR
2.
Decimal to Binary Encoder circuit has 2n (or fewer) inputs that accepts a decimal number and has n outputs to
display the binary equivalent number in bits. Fig. 1 shows a simple encoder that converts decimal digits from 0 to 7 to
their binary equivalents. Construct this encoder and fill up the truth table based given the gates.
Deci
mal
D1
X=
2^2
Y=
2^1
Z=
2^0
Write simplified logical expression for
X, Y, and Z in terms of D’s
X=
D2
D3
Y=
D4
D5
Z=
D6
Fig. 1. Decimal to Binary Encoder.
D7
a. Set all switches to Logical 1. Observe and record
the condition of the LEDs.
Dr. Ali Kujoory
6/30/2016
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b. Set switch 1 to Logical 0, observe and record the
condition of the LEDs.
c. Set switch 1 to Logical 1 and reset switch 2 to (0),
observe and record the conditions of the LEDs.
d. Continue setting one switch to zero at a time and
record the indication of the LEDs. Demonstrate
your circuit to the instructor.
e. Explain the operation of the encoder used by
explaining the operation of each gate.
3.
Binary to Decimal Decoder: When a computer has completed an operation, the answer is usually given in binary
form that has to be decoded to decimal form for most people. A decoder could do this function. It has n inputs and 2 n
outputs. Fig. 2 shows a simple decoder using 3-input NAND gates.
Fig. 2. A 3-bit Binary to Decimal Decoder using 3-input AND
gates (see Fig 4.18 and Table 4.6).
a. Construct the truth table for the decoder to convert the 3bit binary number to its decimal equivalent D0-D7.
2^2
Input binary bits
2^1
2^0
Output Decimal
Digits
D0
D7
b. Explain why decimal digit 0
should be wired the way it is.
c. Explain why decimal digit 5
should be wired the way it is.
4.
Verilog simulation – Write a Verilog design program for the 3-bit to decimal decoder, compile it, make sure it is
error free, and simulate the circuit to get the waveform of the output for the inputs x=y=z=0 initially, after 50 ms,
x=z=0, y=1, after 50 ms, x=1, y=1, z=0, and after 50 ms, x=y=z=1. Show the Verilog programs for the circuit and the
test bench, and the waveforms display for a period of 200 ms in the following table. Verify the output versus the truth
table above. Show the waveform of the inputs and outputs diagrams to the instructor and include in your report.
Verilog Design Program
Verilog Test Bench Program
Verilog waveform Diagram (you can use “Print Screen to copy the waveform)
Dr. Ali Kujoory
6/30/2016
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E. Feedback/Comments (your comments will help improving this lab)
Was the instruction clear enough? Any error?
How difficult was it for you?
Do you have any observations to make?
F. Report
1. In your report, make sure to include the title of the experiment, your & your partners’ names, your group number.
Include your measurements and answers you obtained in the tables above. Do not include the unnecessary parts
such as the objectives, instructions, and procedures.
2. Submit your report to the instructor at the end of the session.
(*) The author acknowledges Mr. S. Marivani as some of the sections come from their work.
Dr. Ali Kujoory
6/30/2016
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