DC to DC Power Converion
R. Ely and M. Garcia-Sciveres
Atlas Upgrade Workshop
Santa Cruz, November 2005
• Series Scheme
• Charge Pumps
• Plans
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
1
Higher voltage power distribution is a MUST
Read: voltage delivery at n times operating voltage
7
6
5
4
3
2
1
0
n=2
n=5
n=8
SCT
SLHC
15.5
14.5
13.5
12.5
11.5
10.5
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
n= 10
0.5
[1+x]/[1 + x/n]
Efficiency ratio: serial over parallel powering
x = IR/V
(from Marc Weber’s Genova workshop talk)
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
2
Two Options
•Serial Power
•Work started with Pixels. Demonstrated with present
modules by Bonn group
•Picked up for SCT modules by Marc Weber at RAL
•Will be incorporated into stave prototypes
•DC-DC converters
•Proposed by LBNL
•Initial simulations shown at Genova (details later)
•No prototype yet due to lack of IC designer availability
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
3
First of all:
Serial powering applies to modules, that is groups of chips on
one hybrid connected to one sensor. Within hybrid, chips are
powered in parallel !
 one current source for a chain of
modules; voltage defined by set of
regulators
 “ground levels” of any pair of
modules vary
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
4
RAL work (Mark Weber)
4 SCT modules, serial powering PCBs, DAQ support cards
M4
M3
DAQ support card
M2
Serial powering
PCB
SCT module 1
Nov. 10, 2005
DAQ support
card
Serial powering
PCB
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
5
Schematics of serial powering PCB
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
6
Photograph of serial powering PCB
Analog regulator
Nov. 10, 2005
AC LVDS Clock
and command
AC LVDS data
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
DAQ support
card
SCT module
Shunt regulator
7
Noise performance: indep. vs. serial powering
Let’s look at noise occupancy (NO) first
Module 662 powered independently
Module 662 powered in series with 3 others
Nov. 10, 2005
UCSC US ATLAS remains
Upgrade meeting excellent
-- Ely, Garcia-Sciveres
Noise performance
!
8
Noise performance: independent powering
vs. serial powering
Independently powered
Powered in series
trimDAC range 0
662
681
755
628
PP
2.04E-06
4.18E-06
1.85E-05
3.90E-05
1.91E-05
5.00E-05
2.99E-05
2.33E-05
PP
2.15E-06
3.88E-06
1.82E-05
3.96E-05
1.82E-05
4.78E-05
2.90E-05
2.25E-05
PP
2.23E-06
3.86E-06
1.74E-05
3.73E-05
1.77E-05
4.58E-05
2.83E-05
2.23E-05
SP4
1.78E-06
3.60E-06
1.03E-05
1.50E-05
1.07E-05
3.19E-05
3.87E-05
3.27E-05
SP4
1.86E-06
3.45E-06
8.94E-06
1.32E-05
9.19E-06
2.74E-05
3.23E-05
2.82E-05
SP4
2.33E-06
4.11E-06
9.62E-06
1.55E-05
9.94E-06
2.96E-05
3.42E-05
2.94E-05
Noise performance remains excellent
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
9
Noise performance: independent powering
vs. serial powering
Independently powered | Powered in series
Noise for IP (1-3) and SP (4-6)
noise occupancy
1.00E-004
1
2
3
4
5
6
755 btm
628 top
1.00E-005
1.00E-006
run nr.
662 top
662 btm
681 top
681 btm
755 top
628 btm
Noise performance remains excellent
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
10
Serial SCT plans from Genova
 More studies on SCT module set-up (1-3 months)
o more noise tests e.g. introducing noise sources/ oscillations
o closer look into AC-LVDS coupling
 Built and study a more realistic system(½ -2 years)
o
o
o
o
o
Dense packaging;
Grounding and shielding issues
Miniaturized regulator circuitry;
Modified readout chip
Redundancy features
 If promising, develop SLHC prototype (> 2 years)
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
11
DC-DC Converter options
• Switched Capacitor array
– not common in industry except for divide by 2
– Seems natural choice for us- fewer worries (see below).
• Inductor Buck converter
– typical in industry
– We would have to worry about magnetic field, EMI from
fringe fields, and would have to make our own air-core
toroidal inductors.
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
12
Divide by 4 Stack
4 capacitors – 13 switches
Vd
1
+
-
+
-
+
-
+
-
• Phase 1
+
-
Vd
Load
1
+
-
• Phase 2
+
-
+
-
1
+
-
+
-
Load
+
-
1
+
-
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
Load
13
DC Converter - DC4x5
DC converter with 4 caps and an ideal conversion ratio of 5
10 switches
1
C3
2
1
C2
2
C1
VS
1
2
Phase 1
C3
3V
5V
Nov. 10, 2005
2V
1
Z
2
C1
C2
C0
Phase 2
V
VS
1
2
C2
C0
V
C3
C1
C0
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
14
DC Converter – Div by 4 Ladder
Phase 1
6 Capacitors
8 Switches
VS
C5
VS
1
2
C3
C4
C1
C2
C5
1
C4
C0
2
C3
1
Phase 2
C2
2
C1
1
C0
Z
C5
C4
C3
C2
C1
C0
2
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
15
Comparison of Circuits
Normalize to Divide by 5
• Stack
5 caps 16 switches
– Uniform charge on caps
– Large voltage swings on switches
• DC4x5 4 caps 10 switches
– 2 caps have potential of 3Vo
– Lower voltage swings on switches
• Ladder
10 caps 12 switches
– Larger potential differences on caps
– Voltage swings on switches ~ Vo
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
16
CMOS Transistor Switches
• Austria Microsystems H35 Process
– Feature size
0.35μ
– 3 gate oxides
– Vds up to 50 vts
– Bulk isolation
– Gate oxide breakdown vt > 8vts
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
17
AMS H35 Transistors
Device
Name
Min. L Max. Max
(μ)
Vgs(vt Vds(vt
)
)
On Res.
L = min
W= 50m
Cg (pf)
NMOSI
0.5
3.6
3.6
0.06
125
NMOS50
T
0.5
3.6
50
0.54
364
PMOS50
T
1.0
3.6
50
0.73
369
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
18
Figures of Merit
(for divide by n)
• Voltage efficiency - εv = n*Vout / Vin
– Vout is a function of the load = Vin / n for no load
• Current efficiency - εI = Iout / n*Iin
– Charge is lost charging the gate capacitance of the switches
• Power efficiency - εp = εv * εI
• Ripple - less than Iout*period/C
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
19
Figures of Merit for Divide by n Stack
Supplying Io
(all switches have ‘on’ resistance R, all switched capacitors have value C
and Co >>C)
• Low frequency limit – RC << 1/f
V
I
V  ns  o
0
nfC
(For ladder)
V nI
V  ns  o
0
nfC
• Hi frequency limit - RC >> 1/f
V 2I R
(n 1)(2n 1)
V  ns  no (1
)
0
n2
V 4I R
 ns  no
for l arg e n
- clearly we want IoR << Vs/4 (for Vs = 10v, R < 2.5Ώ
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
20
Divide by 5 Stack
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
21
Drain-Gate-Source Waveforms of
Switches
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
22
Efficiency versus Frequency
V eff and I eff vs period
1.2
efficiency
1
0.8
V eff
I eff
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
period (us)
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
23
Efficiency vs Transistor Width
Efficiency vs transistor width
1.2
1
V eff 8mhz
efficiency
0.8
V eff 5mhz
Veff 2.5mhz
0.6
Ieff 8mhz
Ieff 5mhz
0.4
Ieff 2.5mhz
0.2
0
0
10
20
30
40
width (mm)
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
24
Power Efficiency
Power Efficiency vs transistor width
0.9
0.8
0.7
efficiency
0.6
Peff 8mz
0.5
Peff 5mhz
0.4
Peff 2.5 mhz
0.3
0.2
0.1
0
0
5
10
15
20
25
30
35
width (mm)
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
25
Buck Converter
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
26
DC Conversion Conclusions
• At an operating freqency of 5mhz
(Co = 4.7uf, C1 = 0.2uf
– Voltage efficiency ~.84
– Current efficiency ~.92
– Ripple = 1.2%
– Output impedance = 0.25 ohms (25mv / 100ma)
• Clock generator will reduce efficiency by 10%
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
27
Other topics not related to power
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
28
Test of Indium Bumped “2E” Assembly
2E = 2 columns per pixel.
Only a small region of the
sensor is properly bonded
to the readout chip. The rest
of the pixels are
disconnected. The bonded
region is shown here. X-axis
is column number and Yaxis is row. Only the bonded
channels were probed in
what follows. Disconnected
channels were masked off.
Nov. 10, 2005
Mask used for scans
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
29
Low voltage values not
reliable due to bad S-
Noise vs. Voltage
curve fits
This is the most probable
single channel noise for
select connected pixels.
Determined from s-curve
fits in charge injection
scans after tuning
thresholds to 4000e.
Looks like
Depletion voltage at ~23
V
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
30
Representive S-curves at varying voltages
Above
depletioon
voltage (~25 V)
12 V
6.5 V
3.5 V
2.0 V
Corrected bias voltage
Nov. 10, 2005
0.5 V
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
31
Short strip module geometry
For a given hybrid technology, only way to reduce
ratio (hybrid_mass)/(silicon mass) is to increase IC
input density
Hybrid can neck down
here to save mass
Sensor is twice the strip length,
With bond pads in the middle.
IC
hybrid
sensor
stave
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
32
Nanowire carpet hybrid pixel proposal
•
•
•
•
Submitted to
LBNL molecular
foundry
Too recent to
know where this
will go
Eliminates
bump bonding
AND sensor
wafer
patterning.
Intent is to
produce very
cheap hybrid
pixel modules.
Nov. 10, 2005
UCSC US ATLAS Upgrade meeting -- Ely, Garcia-Sciveres
33