ENEE 408C Lab
Capstone Project: Digital System
Design
Spring 2006
Class Web Site:
http://www.ece.umd.edu/class/enee408c
TA’s Information
Alessandro Geist
ageist@umd.edu
Office Hours: TBD
Cyclic Behavioral Models
Model both level-sensitive behavior (combinational) and
edge-sensitive behavior (flip-flop) of an element.
always@ (a or b) begin
sum = a ^ b;
c_out = a & b;
end
always@ (posedge clk)
dff_out <= dff_in;
Blocking vs. Nonblocking
In always blocks
Blocking
– Execute in order
– Better for combinational logic
Nonblocking
– Execute Concurrently (in parallel)
– Better for sequential logic
– RHS of all statements calculated first from
values before execution
Combinational Examples of
Blocking vs. Nonblocking
Blocking
Reg D, B;
always @ (E or D) begin
// D=2, E=5, B=3 initially
D = E; // D=5
B = D; // B=5
end
Nonblocking
Reg D, B;
always @ (E or D) begin
// D=2, E=5, B=3 initially
D <= E; // D=5
B <= D; // B=2
end
Data Types — Registers
A register is a data storage element that
retains its value until another value is
placed on it. Like a Variable
NOT A FLIP-FLOP
– Flip-flops are synchronous.
– Registers can be set at any time.
Registers
– Set by other registers, from wires, or from
constants
– Default to x.
Operators — Conditional
?:
cond_expr ? expr1 : expr2
– wire[0:2] STUDENT =
MARKS > 75 ? GRADE_A : GRADE_C ;
– always
#5 CTR = (CTR != 25) ? (CTR + 1) : 5 ;
If cond_expr is an x or a z, the result is
a bitwise operation on expr1 and expr2.
– 0 with 0 gives 0, 1 with 1 gives 1, the rest
are x.
“If” Statement
Behavioral code
Must be contained within an “always” block
If statement is incomplete (not all cases handled) will result in
inference of a transparent latch in hardware
Syntax:
reg a;
always @ (sel or b)
begin
if (sel == 1)
a = b;
end
While sel is high, a will follow b. When sel is low, a will remain constant
“If-else” Statements
always @ (sel or b or c)
begin
if (sel == 1)
a = c;
else
a=b;
end
“If” Statements
Remember we are designing hardware and
nonblocking more closely resembles actual hardware
reg a, x;
always @ (sel or b or c or d or e) begin
if (sel == 1) begin
a <= c;
x <= d | a;
end
else begin
a <= b;
x <= e;
end
end
D-type Flip-Flop
module registerDFF(Q,D, clk, reset_n);
output
Q;
// the 1-bit output bus
input
input
input
D;
// the 1-bit input data bus
clk;
reset_n; // active low reset signal
reg
Q;
// must be a register so it can hold a value
always @ (posedge clk or negedge reset_n) begin
if (!reset_n)
// active low reset
Q<=1'b0;
else
Q<=D;
// otherwise it's a positive edge of clk so Q is updated to D.
end
endmodule
Transparent Latches
When the circuit is synthesized
Formed when not all possibilities are
specified
Case Statements
Case statement executes first match
found and does not consider remaining
possibilities
Default case allows capture of remaining
cases
Usually used to generate a multiplexer
(MUX)
Case Statements
module ALU(alu_out, Opcode, A, B);
output [7:0] alu_out;
input
[3:0] Opcode;
input
[7:0] A, B;
reg
[7:0] alu_out;
always @ (Opcode or A or B) begin
case (Opcode)
4’b0000:
alu_out = 0;
4’b0001:
alu_out = A+B;
4’b0010:
alu_out = A-B;
4’b0011:
alu_out = A & B;
4’b0100:
alu_out = ~B;
default:
alu_out = 0;
endcase
endmodule
// NOP
// ADD
// SUB
// AND
// NOT
Case Statements
parameter NOP =
4’b0000;
parameter ADD =
4’b0001;
parameter SUB =
4’b0010;
parameter AND =
4’b0011;
parameter NOT =
4’b0100;
…
always @ (Opcode or A or B) begin
case (Opcode)
NOP:
alu_out = 0;
// NOP
ADD:
alu_out = A+B;
// ADD
SUB:
alu_out = A-B;
// SUB
AND:
alu_out = A & B;// AND
…
Lexical Tokens
Verilog source files consist of streams
of lexical tokens separated by white
space.
Types of lexical tokens:
white space (newline, tab, space)
comments
operators
numbers
strings
identifiers (case sensitive)
keywords (lower case)
Lexical Conventions
White space :
Ignored in Verilog except when separating
tokens. Not ignored in strings.
Comments (like C++, Java):
– Single Line //
– Multiple Lines /* … */
Use comments abundantly and
meaningfully!
Operators — Arithmetic
Binary operators (e.g., c = a * b) :
Multiply (*)
Divide (/)
Add (+)
Subtract (-)
Modulus (%)
Power (**)
Unary operators:
Unary plus (+)
Unary minus (-)
Operators — Relational
> (greater than)
< (less than)
>= (greater than or equal to)
<= (less than or equal to)
Operators — Equality
==, != (logical equality, inequality)
– Yields an x if either operand has an x or z in
it.
===, !== (case equality, inequality)
– Checks x’s and z’s for equality.
Operators — Logical
Logical Operators
!
&&
||
!m
Is m not true? (1bit True/False
result)
m && n
Are both m and n
true? (1-bit
True/False result)
m || n
Are either m or n
true? (1-bit
True/False result)
Operators — Bitwise
Bitwise Operators
~
~m
&
m&n
AND each bit of m with
each bit of n
|
m|n
OR each bit of m with
each bit of n
^
m^n
Exclusive OR each bit of
m with n
~^
^~
m ~^ n
m ^~ n
Exclusive NOR each bit
of m with n
Invert each bit of m
Unary Reduction Operators
&
~&
|
~|
&m
AND all bits in m
together (1-bit result)
~&m
NAND all bits in m
together (1-bit result)
|m
OR all bits in m
together (1-bit result)
~|m
NOR all bits in m
together (1-bit result)
Exclusive OR all bits in
m (1-bit result)
^m
~^m
Exclusive NOR all bits in
m (1-bit result)
^~m
These operators operate on all bits of a
single operand and produce a 1-bit result.
^
~^
^~
Operators — Concatenation and
Replication
{} - concatenation
– {a,b} is the concatenation of a and b
– if a and b are 10 bits, {a,b} is 20 bits
{ %d {} } - Replication inside
concatenation
– {5 {a}} is the same as {a,a,a,a,a}
Operators — Shift
>> (right shift) Vacated bit positions filled with
zeros
<< (left shift) Vacated bit positions filled with
zeros
Example: A = A << 2; shifts A two bits to left
with zero fill.
Arithmetic shifts:
>>>
<<<
(same as <<)
Operators — Conditional
?:
cond_expr ? expr1 : expr2
– wire[0:2] STUDENT =
MARKS > 75 ? GRADE_A : GRADE_C ;
– always
#5 CTR = (CTR != 25) ? (CTR + 1) : 5 ;
If cond_expr is an x or a z, the result is
a bitwise operation on expr1 and expr2.
– 0 with 0 gives 0, 1 with 1 gives 1, the rest
are x.