ENEE 408C Lab Spring 2006 Capstone Project: Digital System Design Class Web Site:

ENEE 408C Lab
Capstone Project: Digital System Design
Spring 2006
Class Web Site:
Who & Where is my TA?
Lin Yuan
[email protected]
Phone: (240) 383-0900
Office: 1454 AVW
Office Hours: Fri 1-3pm
send me an email before coming to my office
What do we do in lab session?
Review of lecture
 In-class quizzes
 Q &A
 Teamwork on projects
What software shall we use?
Windows XP or UNIX in GLUE/WAM Lab
 Xilinx ISE project navigator
 ModelSim Simulator
 Cadence NC-Verilog
How to submit our works?
Send an email to [email protected] with
the subject line:
– For homework: hw#
– For quiz: quiz#
– For project: proj#_<yourLastName>
What are you expected to know?
Number system in computers
Boolean logic expression and optimization
Karnaugh map and other optimization techniques
finite state machine minimization and encoding
Basic ALUs in computers
adders, multiplexers, multipliers, dividers, decoders,
encoders, registers etc.
Basic programming skills
What will be a PLUS if you know?
Hardware design languages (HDL)
– VHDL, AHDL, Verilog etc.
Field Programming Gate Array (FPGA)
 Electronic Design Automation (EDA) tools
 Digital signal processing
What will you learn?
Digital system (hardware) design process
Design description ? Yes
Synthesis ? Yes
Implementation ? Yes (but restricted to FPGA only)
Fabrication ? No
Use of design tools
Verilog HDL language
Industry standard simulation and synthesis tools
Xilinx FPGA design flow
Spirit of teamwork
What do we do today?
Introduce yourself
 Make friends with your future teammates
and your TA
 Get familiar with the software and
operating system
 Watch a demo of FPGA software
What will we do next week?
Introduction of Verilog HDL
 Writing and simulating Verilog codes
 Probably the first in-class quiz (will let
you know one day before the class)
Any other questions?
See you next week!