inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture 18
CPU Design: The Single-Cycle I
2010-07-21
Instructor Paul Pearce
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CS61C L18 CPU Design: The Single-Cycle I (1)
Pearce, Summer 2010 © UCB
+4
1. Instruction
Fetch
ALU
Data
memory
rd
rs
rt
registers
PC
instruction
memory
In Review: Generic Steps of Datapath
imm
2. Decode/
Register
Read
CS61C L18 CPU Design: The Single-Cycle I (2)
3. Execute 4. Memory
5. Reg.
Write
Pearce, Summer 2010 © UCB
Datapath Walkthroughs (1/3)
• add
$3,$1,$2 # R[3] = R[1]+R[2]
• Stage 1: fetch this instruction, inc. PC
• Stage 2: decode to find it’s an add, then read
registers $1 and $2
• Stage 3: add the two values retrieved in Stage
2
• Stage 4: idle (nothing to write to memory)
• Stage 5: write result of Stage 3 into register $3
CS61C L18 CPU Design: The Single-Cycle I (3)
Pearce, Summer 2010 © UCB
+4
2
reg[1]
reg[2]
reg[1]+reg[2]
ALU
Data
memory
3
1
registers
PC
instruction
memory
Example: add Instruction
imm
add $3, $1, $2
CS61C L18 CPU Design: The Single-Cycle I (4)
Pearce, Summer 2010 © UCB
Datapath Walkthroughs (2/3)
• slti
$3,$1,17
• Stage 1: fetch this instruction, inc. PC
• Stage 2: decode to find it’s an slti, then read
register $1
• Stage 3: compare value retrieved in Stage 2 with
the integer 17
• Stage 4: idle
• Stage 5: write the result of Stage 3 in register $3
CS61C L18 CPU Design: The Single-Cycle I (5)
Pearce, Summer 2010 © UCB
Example: slti Instruction
+4
imm
17
x
1
reg[1]
ALU
Data
memory
3
registers
PC
instruction
memory
reg[1]<17?
slti $3, $1, 17
CS61C L18 CPU Design: The Single-Cycle I (6)
Pearce, Summer 2010 © UCB
Datapath Walkthroughs (3/3)
• sw
$3, 17($1)
• Stage 1: fetch this instruction, inc. PC
• Stage 2: decode to find it’s a sw, then read
registers $1 and $3
• Stage 3: add 17 to value in register $1
(retrieved in Stage 2)
• Stage 4: write value in register $3
(retrieved in Stage 2) into memory address
computed in Stage 3
• Stage 5: idle (nothing to write into a
register)
CS61C L18 CPU Design: The Single-Cycle I (7)
Pearce, Summer 2010 © UCB
+4
imm
17
x
1
SW $3, 17($1)
CS61C L18 CPU Design: The Single-Cycle I (8)
reg[1]
reg[3]
reg[1]+17
ALU
Data
memory
3
registers
PC
instruction
memory
Example: sw Instruction
MEM[$1+17]=$3
Pearce, Summer 2010 © UCB
Why Five Stages? (1/2)
• Could we have a different number of
stages?
• Yes, and other architectures do
• So why does MIPS have five if
instructions tend to idle for at least
one stage?
• The five stages are the union of all the
operations needed by all the
instructions.
• There is one instruction that uses all five
stages: the load
CS61C L18 CPU Design: The Single-Cycle I (9)
Pearce, Summer 2010 © UCB
Why Five Stages? (2/2)
• lw
$3, 17($1)
• Stage 1: fetch this instruction, inc. PC
• Stage 2: decode to find it’s a lw, then read
register $1
• Stage 3: add 17 to value in register $1
(retrieved in Stage 2)
• Stage 4: read value from memory address
compute in Stage 3
• Stage 5: write value found in Stage 4 into
register $3
CS61C L18 CPU Design: The Single-Cycle I (10)
Pearce, Summer 2010 © UCB
Example: lw Instruction
+4
imm
17
x
1
reg[1]
ALU
Data
memory
3
registers
PC
instruction
memory
reg[1]+17
MEM[$1+17]
lw $3, 17($1)
CS61C L18 CPU Design: The Single-Cycle I (11)
Pearce, Summer 2010 © UCB
Datapath Summary
• The datapath based on data transfers
required to perform instructions
+4
ALU
Data
memory
rd
rs
rt
registers
PC
instruction
memory
• A controller causes the right transfers
to happen
imm
opcode, funct
Controller
CS61C L18 CPU Design: The Single-Cycle I (12)
Pearce, Summer 2010 © UCB
Peer Instruction
A. If the destination reg is the same
as the source reg, we could
compute the incorrect value!
B. We’re going to be able to read 2
registers and write a 3rd in 1 cycle
CS61C L18 CPU Design: The Single-Cycle I (13)
A:
B:
C:
D:
AB
FF
FT
TF
TT
Pearce, Summer 2010 © UCB
Administrivia
• Homework 6 due tonight
• Homework 7 due Saturday
• Midterm grades are in glookup
• Anything else?
CS61C L18 CPU Design: The Single-Cycle I (15)
Pearce, Summer 2010 © UCB
For each instruction, how do we
control the flow of information
though the datapath?
CPU clocking (1/2)
• Single Cycle CPU: All stages of an
instruction are completed within one
long clock cycle.
• The clock cycle is made sufficient long to
allow each instruction to complete all
stages without interruption and within
one cycle.
1. Instruction
Fetch
2. Decode/
Register
Read
3. Execute 4. Memory
CS61C L17 Combinational Logic Blocks and Intro to CPU Design (16)
5. Reg.
Write
Pearce, Summer 2010 © UCB
CPU clocking (2/2)
For each instruction, how do we
control the flow of information
though the datapath?
• Multiple-cycle CPU: Only one stage of
instruction per clock cycle.
• The clock is made as long as the slowest
stage.
1. Instruction 2. Decode/
3. Execute
Fetch
Register
Read
4. Memory
5. Reg.
Write
• Several significant advantages over
single cycle execution: Unused stages in
a particular instruction can be skipped
OR instructions can be pipelined
(overlapped).
CS61C L17 Combinational Logic Blocks and Intro to CPU Design (17)
Pearce, Summer 2010 © UCB
How to Design a Processor: step-by-step
1. Analyze instruction set architecture (ISA)
 datapath requirements
1. meaning of each instruction is given by the register
transfers
2. datapath must include storage element for ISA registers
3. datapath must support each register transfer
2. Select set of datapath components and establish
clocking methodology
3. Assemble datapath meeting requirements
4. Analyze implementation of each instruction to
determine setting of control points that effects
the register transfer.
5. Assemble the control logic
CS61C L18 CPU Design: The Single-Cycle I (18)
Pearce, Summer 2010 © UCB
Review: The MIPS Instruction Formats
• All MIPS instructions are 32 bits long. 3 formats:
• R-type
31
26
op
rs
6 bits
31
• I-type
26
op
31
16
rt
5 bits
5 bits
21
rs
6 bits
• J-type
21
5 bits
11
6
0
rd
shamt
funct
5 bits
5 bits
6 bits
16
0
address/immediate
rt
5 bits
16 bits
26
op
6 bits
0
target address
26 bits
• The different fields are:
•
•
•
•
•
•
op: operation (“opcode”) of the instruction
rs, rt, rd: the source and destination register specifiers
shamt: shift amount
funct: selects the variant of the operation in the “op” field
address / immediate: address offset or immediate value
target address: target address of jump instruction
CS61C L18 CPU Design: The Single-Cycle I (19)
Pearce, Summer 2010 © UCB
Step 1a: The MIPS-lite Subset for today
• ADDU and SUBU
31
•addu rd,rs,rt
op
31
• LOAD and
STORE Word
31
6 bits
0
rd
shamt
funct
5 bits
5 bits
6 bits
0
16 bits
16
rt
5 bits
6
immediate
5 bits
21
rs
11
16
rt
5 bits
26
op
5 bits
21
rs
6 bits
16
rt
5 bits
26
op
•ori rt,rs,imm16
21
rs
6 bits
•subu rd,rs,rt
• OR Immediate:
26
0
immediate
5 bits
16 bits
•lw rt,rs,imm16
•sw rt,rs,imm16 31
• BRANCH:
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
•beq rs,rt,imm16
CS61C L18 CPU Design: The Single-Cycle I (20)
Pearce, Summer 2010 © UCB
Register Transfer Language (RTL)
• RTL gives the meaning of the instructions
{op , rs , rt , rd , shamt , funct}  MEM[ PC ]
{op , rs , rt , Imm16}  MEM[ PC ]
• All start by fetching the instruction
inst
Register Transfers
ADDU
R[rd]  R[rs] + R[rt];
PC  PC + 4
SUBU
R[rd]  R[rs] – R[rt];
PC  PC + 4
ORI
R[rt]  R[rs] | zero_ext(Imm16);
PC  PC + 4
LOAD
R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4
STORE
MEM[ R[rs] + sign_ext(Imm16) ]  R[rt]; PC  PC + 4
BEQ if ( R[rs] == R[rt] ) then
PC  PC + 4 + (sign_ext(Imm16) || 00)
else PC  PC + 4
CS61C L18 CPU Design: The Single-Cycle I (21)
Pearce, Summer 2010 © UCB
Step 1: Requirements of the Instruction Set
• Memory (MEM)
• instructions & data (will use one for each)
• Registers (R: 32 x 32)
• read RS
• read RT
• Write RT or RD
• PC
• Extender (sign/zero extend)
• Add/Sub/OR unit for operation on register(s) or
extended immediate
• Add 4 (+ maybe extended immediate) to PC
• Compare registers?
CS61C L18 CPU Design: The Single-Cycle I (22)
Pearce, Summer 2010 © UCB
Step 2: Components of the Datapath
• Combinational Elements
• Storage Elements
• Clocking methodology
CS61C L18 CPU Design: The Single-Cycle I (23)
Pearce, Summer 2010 © UCB
Combinational Logic Elements (Building Blocks)
• Adder
CarryIn
A
B
Adder
32
Sum
32
Overflow
32
Select
32
B
MUX
• MUX
A
32
A
B
32
CS61C L18 CPU Design: The Single-Cycle I (24)
OP
??
ALU
• ALU
32
Y
32
32
Result
zero?
Pearce, Summer 2010 © UCB
ALU Needs for MIPS-lite + Rest of MIPS
• Addition, subtraction, logical OR, ==:
ADDU
R[rd] = R[rs] + R[rt]; ...
SUBU
R[rd] = R[rs] – R[rt]; ...
ORI
R[rt] = R[rs] |
zero_ext(Imm16)...
BEQ
if ( R[rs] == R[rt] )...
• Test to see if output == 0 for any ALU
operation gives == test. How?
• P&H also adds AND,
Set Less Than (1 if A < B, 0 otherwise)
• ALU taken from chapter 4 (4th edition),
chapter 5 (3rd edition)
CS61C L18 CPU Design: The Single-Cycle I (25)
Pearce, Summer 2010 © UCB
What Hardware Is Needed? (1/2)
• PC: a register which keeps track of
memory addr of the next instruction
• General Purpose Registers
• used in Stages 2 (Read) and 5 (Write)
• MIPS has 31 of these (plus $0)
• Memory
• used in Stages 1 (Fetch) and 4 (R/W)
• cache system makes these two stages as
fast as the others, on average
CS61C L18 CPU Design: The Single-Cycle I (26)
Pearce, Summer 2010 © UCB
What Hardware Is Needed? (2/2)
• ALU
• used in Stage 3
• something that performs all necessary
functions: arithmetic, logicals, etc.
• we’ll design details later
• Miscellaneous Registers
• In implementations with only one stage per
clock cycle, registers are inserted between
stages to hold intermediate data and control
signals as they travels from stage to stage.
• Note: Register is a general purpose term
meaning something that stores bits. Not all
registers are in the “register file”.
CS61C L18 CPU Design: The Single-Cycle I (27)
Pearce, Summer 2010 © UCB
Storage Element: Idealized Memory
• Memory (idealized)
• One input bus: Data In
• One output bus: Data Out
• Memory word is found by:
Write Enable
Address
Data In
32
Clk
DataOut
32
• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memory
word to be written via the Data In bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational
logic block:
 Address valid  Data Out valid after “access time.”
CS61C L18 CPU Design: The Single-Cycle I (28)
Pearce, Summer 2010 © UCB
Storage Element: Register (Building Block)
• Similar to D Flip Flop except
• N-bit input and output
• Write Enable input
• Write Enable:
• negated (or deasserted) (0):
Data Out will not change
Write Enable
Data In
Data Out
N
N
clk
• asserted (1):
Data Out will become Data In on positive
edge of clock
CS61C L18 CPU Design: The Single-Cycle I (29)
Pearce, Summer 2010 © UCB
Storage Element: Register File
• Register File consists of 32 registers:
• Two 32-bit output busses:
busA and busB
• One 32-bit input bus: busW
RW RA RB
Write Enable 5 5 5
busA
32
busW
32 32-bit
32
Registers busB
• Register is selected by:
Clk
32
• RA (number) selects the register to put on busA (data)
• RB (number) selects the register to put on busB (data)
• RW (number) selects the register to be written
via busW (data) when Write Enable is 1
• Clock input (clk)
• The clk input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic
block:

RA or RB valid  busA or busB valid after “access time.”
CS61C L18 CPU Design: The Single-Cycle I (30)
Pearce, Summer 2010 © UCB
Step 3: Assemble DataPath meeting requirements
• Register Transfer Requirements
 Datapath Assembly
• Lets start by analyzing the following
Register Transfer Requirements, and
build our datapath piece by piece
based on those requirements
• Instruction Fetch
• add / subtract
• We’ll do the rest next time.
CS61C L18 CPU Design: The Single-Cycle I (31)
Pearce, Summer 2010 © UCB
3a: Overview of the Instruction Fetch Unit
• The common RTL operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
 Sequential Code: PC  PC + 4
 Branch and Jump: PC  “something else”
clk
PC
Next Address
Logic
Address
Instruction
Memory
CS61C L18 CPU Design: The Single-Cycle I (32)
Instruction Word
32
Pearce, Summer 2010 © UCB
3b: Add & Subtract
• R[rd] = R[rs] op R[rt] (addu rd,rs,rt)
• Ra, Rb, and Rw come from instruction’s Rs, Rt,
and Rd fields 31
26
21
16
11
6
op
6 bits
rs
5 bits
rt
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
0
• ALUctr and RegWr: control logic after
decoding the instruction
Rd Rs Rt
RegWr 5 5 5
Rw Ra Rb
32 32-bit
Registers
clk
busA
32
busB
ALU
busW
32
ALUctr
Result
32
32
… Already defined the register file & ALU
CS61C L18 CPU Design: The Single-Cycle I (33)
Pearce, Summer 2010 © UCB
Peer Instruction
1) We should use the main ALU to
compute PC=PC+4
2) The ALU is inactive for memory
reads or writes.
a)
b)
c)
d)
e)
123
FFF
FFT
FTF
TFT
TTT
3) The ALU is a synchronous device
CS61C L18 CPU Design: The Single-Cycle I (34)
Pearce, Summer 2010 © UCB
Peer Instruction Answer
1) We should use the main ALU to
compute PC=PC+4
2) The ALU is inactive for memory
reads or writes.
a)
b)
c)
d)
e)
123
FFF
FFT
FTF
TFT
TTT
3) The ALU is a synchronous device
CS61C L18 CPU Design: The Single-Cycle I (35)
Pearce, Summer 2010 © UCB
How to Design a Processor: step-by-step
1. Analyze instruction set architecture (ISA)
 datapath requirements
1. meaning of each instruction is given by the register
transfers
2. datapath must include storage element for ISA registers
3. datapath must support each register transfer
2. Select set of datapath components and establish
clocking methodology
3. Assemble datapath meeting requirements
4. Analyze implementation of each instruction to
determine setting of control points that effects
the register transfer.
5. Assemble the control logic
CS61C L18 CPU Design: The Single-Cycle I (36)
Pearce, Summer 2010 © UCB