inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture #22 – Pipelining II, Cache I
2008-7-29
Wireworld circuits
http://www.maa.org/editorial/mathgames/mathgames_05_24_04.html
http://www.quinapalus.com/wi-index.html
Albert Chae, Instructor
CS61C L22 Pipelining II, Cache I (1)
Chae, Summer 2008 © UCB
Review: Processor Pipelining (1/2)
• “Pipeline registers” are added to the
datapath/controller to neatly divide the
single cycle processor into “pipeline
stages”.
• Optimal Pipeline
• Each stage is executing part of an instruction
each clock cycle.
• One inst. finishes during each clock cycle.
• On average, execute far more quickly.
• What makes this work well?
• Similarities between instructions allow us to use
same stages for all instructions (generally).
• Each stage takes about the same amount of time
as all others: little wasted time.
CS61C L22 Pipelining II, Cache I (2)
Chae, Summer 2008 © UCB
A pipelined datapath
From P&H
CS61C L22 Pipelining II, Cache I (3)
Chae, Summer 2008 © UCB
Review: Pipeline (2/2)
• Pipelining is a BIG IDEA
• widely used concept
• What makes it less than perfect?
• Structural hazards: Conflicts for resources.
Suppose we had only one cache?
 Need more HW resources
• Control hazards: Branch instructions effect
which instructions come next.
 Delayed branch
• Data hazards: Data flow between
instructions. Forwarding
CS61C L22 Pipelining II, Cache I (4)
Chae, Summer 2008 © UCB
Review
• Some fixes to hazards
• Illusion of two memories
• Register file convention
• Forwarding
• Load delay slot
• All else fails, bubble/stall
• Latency vs throughput
• What prevents us from getting n-times
speedup, where n is the number of
pipeline stages?
CS61C L22 Pipelining II, Cache I (5)
Chae, Summer 2008 © UCB
Graphical Pipeline Representation
(In Reg, right half highlight read, left half write)
Time (clock cycles)
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
D$
Reg
I$
Reg
ALU
CS61C L22 Pipelining II, Cache I (6)
Reg
ALU
I$
D$
ALU
Reg
ALU
I$
ALU
I
n
s Load
t Add
r.
Store
O
Sub
r
d Or
e
r
D$
Reg
Chae, Summer 2008 © UCB
Control Hazard: Branching (1/8)
Time (clock cycles)
ALU
I
n
I$
D$
Reg
Reg
beq
s
I$
D$
Reg
Reg
t Instr 1
r.
I$
D$
Reg
Reg
Instr 2
O
I$
D$
Reg
Reg
Instr 3
r
I$
D$
Reg
Reg
d Instr 4
e
r
Where do we do the compare for the branch?
ALU
ALU
ALU
ALU
CS61C L22 Pipelining II, Cache I (7)
Chae, Summer 2008 © UCB
Control Hazard: Branching (2/8)
• We had put branch decision-making
hardware in ALU stage
• therefore two more instructions after the
branch will always be fetched, whether or
not the branch is taken
• Desired functionality of a branch
• if we do not take the branch, don’t waste
any time and continue executing
normally
• if we take the branch, don’t execute any
instructions after the branch, just go to
the desired label
CS61C L22 Pipelining II, Cache I (8)
Chae, Summer 2008 © UCB
Control Hazard: Branching (3/8)
• Initial Solution: Stall until decision is
made
• insert “no-op” instructions (those that
accomplish nothing, just take time) or
hold up the fetch of the next instruction
(for 2 cycles).
• Drawback: branches take 3 clock cycles
each (assuming comparator is put in
ALU stage)
CS61C L22 Pipelining II, Cache I (9)
Chae, Summer 2008 © UCB
Control Hazard: Branching (4/8)
• Optimization #1:
• insert special branch comparator in
Stage 2
• as soon as instruction is decoded
(Opcode identifies it as a branch),
immediately make a decision and set the
new value of the PC
• Benefit: since branch is complete in
Stage 2, only one unnecessary
instruction is fetched, so only one no-op
is needed
• Side Note: This means that branches are
idle in Stages 3, 4 and 5.
CS61C L22 Pipelining II, Cache I (10)
Chae, Summer 2008 © UCB
Control Hazard: Branching (5/8)
Time (clock cycles)
ALU
I
n
I$
D$
Reg
Reg
beq
s
I$
D$
Reg
Reg
t Instr 1
r.
I$
D$
Reg
Reg
Instr 2
O
I$
D$
Reg
Reg
Instr 3
r
I$
D$
Reg
Reg
d Instr 4
e
r
Branch comparator moved to Decode stage.
ALU
ALU
ALU
ALU
CS61C L22 Pipelining II, Cache I (11)
Chae, Summer 2008 © UCB
Control Hazard: Branching (6a/8)
Time (clock cycles)
beq
Reg
I$
D$
Reg
Reg
ALU
add
I$
ALU
I
n
s
t
r.
• User inserting no-op instruction
D$
Reg
ALU
bub bub bub bub bub
O nop
ble
ble
ble
ble
ble
r
D$
Reg
Reg
I$
d lw
e
r • Impact: 2 clock cycles per branch
instruction  slow
CS61C L22 Pipelining II, Cache I (12)
Chae, Summer 2008 © UCB
Control Hazard: Branching (6b/8)
Time (clock cycles)
beq
Reg
I$
D$
Reg
Reg
ALU
add
I$
ALU
I
n
s
t
r.
• Controller inserting a single bubble
D$
Reg
ALU
bub
O lw
D$
Reg
Reg
I$
ble
r
d
e
r • Impact: 2 clock cycles per branch
instruction  slow
CS61C L22 Pipelining II, Cache I (13)
Chae, Summer 2008 © UCB
Control Hazard: Branching (7/8)
• Optimization #2: Redefine branches
• Old definition: if we take the branch,
none of the instructions after the branch
get executed by accident
• New definition: whether or not we take
the branch, the single instruction
immediately following the branch gets
executed (called the branch-delay slot)
• The term “Delayed Branch” means
we always execute inst after branch
• This optimization is used on the MIPS
CS61C L22 Pipelining II, Cache I (14)
Chae, Summer 2008 © UCB
Control Hazard: Branching (8/8)
• Notes on Branch-Delay Slot
• Worst-Case Scenario: can always put a
no-op in the branch-delay slot
• Better Case: can find an instruction
preceding the branch which can be
placed in the branch-delay slot without
affecting flow of the program
- re-ordering instructions is a common
method of speeding up programs
- compiler must be very smart in order to find
instructions to do this
- usually can find such an instruction at least
50% of the time
- Jumps also have a delay slot…
CS61C L22 Pipelining II, Cache I (15)
Chae, Summer 2008 © UCB
Example: Nondelayed vs. Delayed Branch
Nondelayed Branch
or
$8, $9 ,$10
Delayed Branch
add $1 ,$2,$3
add $1 ,$2,$3
sub $4, $5,$6
sub $4, $5,$6
beq $1, $4, Exit
beq $1, $4, Exit
or
xor $10, $1,$11
xor $10, $1,$11
Exit:
CS61C L22 Pipelining II, Cache I (16)
$8, $9 ,$10
Exit:
Chae, Summer 2008 © UCB
Out-of-Order Laundry: Don’t Wait
6 PM 7
T
a
s
k
8
9
3030 30 30 30 30 30
A
10
11
12
1
2 AM
Time
bubble
B
C
O
D
r
d E
e
r F
A depends on D; rest continue; need
more resources to allow out-of-order
CS61C L22 Pipelining II, Cache I (17)
Chae, Summer 2008 © UCB
Superscalar Laundry: Parallel per stage
6 PM 7
T
a
s
k
8
9
3030 30 30 30
A
B
C
O
D
r
d E
e
r F
10
11
12
1
2 AM
Time
(light clothing)
(dark clothing)
(very dirty clothing)
(light clothing)
(dark clothing)
(very dirty clothing)
More resources, HW to match mix of
parallel tasks?
CS61C L22 Pipelining II, Cache I (18)
Chae, Summer 2008 © UCB
Superscalar Laundry: Mismatch Mix
6 PM 7
T
a
s
k
8
9
3030 30 30 30 30 30
A
O
r B
d C
e
r
D
10
11
12
1
2 AM
Time
(light clothing)
(light clothing)
(dark clothing)
(light clothing)
Task mix underutilizes extra resources
CS61C L22 Pipelining II, Cache I (19)
Chae, Summer 2008 © UCB
Real-world pipelining problem
• You’re the manager of a HUGE
assembly plant to build computers.
Box
• Main pipeline
• 10 minutes/
pipeline stage
• 60 stages
• Latency: 10hr
CS61C L22 Pipelining II, Cache I (20)
Problem:
need to
run 2 hr
test before
done..help!
Chae, Summer 2008 © UCB
Real-world pipelining problem solution 1
• You remember: “a pipeline frequency
is limited by its slowest stage”, so…
Box
• Main pipeline
• 10
minutes/
2hours/
pipeline stage
• 60 stages
• Latency: 120hr
10hr
CS61C L22 Pipelining II, Cache I (21)
Problem:
need to
run 2 hr
test before
done..help!
Chae, Summer 2008 © UCB
Real-world pipelining problem solution 2
• Create a sub-pipeline!
Box
• Main pipeline
• 10 minutes/
pipeline stage
• 60 stages
CS61C L22 Pipelining II, Cache I (22)
2hr test
(12 CPUs
in this
pipeline)
Chae, Summer 2008 © UCB
Peer Instruction (1/2)
Assume 1 instr/clock, delayed branch, 5 stage
pipeline, forwarding, interlock on unresolved
load hazards (after 103 loops, so pipeline full)
Loop:
lw
addu
sw
addiu
bne
nop
$t0,
$t0,
$t0,
$s1,
$s1,
0($s1)
$t0, $s2
0($s1)
$s1, -4
$zero, Loop
•How many pipeline stages (clock cycles) per
loop iteration to execute this code?
CS61C L22 Pipelining II, Cache I (23)
1
2
3
4
5
6
7
8
9
10
Chae, Summer 2008 © UCB
Peer Instruction Answer (1/2)
• Assume 1 instr/clock, delayed branch, 5
stage pipeline, forwarding, interlock on
unresolved load hazards. 103 iterations,
so pipeline full.
(data hazard so stall)
Loop: 1. lw
$t0,2. 0($s1)
3. addu $t0, $t0, $s2
sw
$t0, 0($s1)
4. addiu $s1, $s1, -4 6. (!= in DCD)
5.
$s1, $zero, Loop
7. bne
8. nop (delayed branch so exec. nop)
• How many pipeline stages (clock cycles)
per loop iteration to execute this code?
1
2
3
CS61C L22 Pipelining II, Cache I (24)
4
5
6
7
8
9
10
Chae, Summer 2008 © UCB
Peer Instruction (2/2)
Assume 1 instr/clock, delayed branch, 5 stage
pipeline, forwarding, interlock on unresolved
load hazards (after 103 loops, so pipeline full).
Rewrite this code to reduce pipeline stages
(clock cycles) per loop to as few as possible.
Loop:
lw
addu
sw
addiu
bne
nop
$t0,
$t0,
$t0,
$s1,
$s1,
0($s1)
$t0, $s2
0($s1)
$s1, -4
$zero, Loop
•How many pipeline stages (clock cycles) per
loop iteration to execute this code?
CS61C L22 Pipelining II, Cache I (25)
1
2
3
4
5
6
7
8
9
10
Chae, Summer 2008 © UCB
Peer Instruction (2/2) How long to execute?
• Rewrite this code to reduce clock cycles
per loop to as few as possible:
Loop: 1. lw
2. addiu
3. addu
4. bne
5. sw
hazard since extra cycle)
$t0,(no0($s1)
$s1, $s1, -4
$t0, $t0, $s2
$s1, $zero, Loop
$t0, +4($s1)
(modified sw to put past addiu)
• How many pipeline stages (clock cycles)
per loop iteration to execute your revised
code? (assume pipeline is full)
1
2
3
CS61C L22 Pipelining II, Cache I (26)
4
5
6
7
8
9
10
Chae, Summer 2008 © UCB
Administrivia
• HW5 due TODAY 7/29
• Quiz9 due Wednesday 7/30
• HW6 due Friday 8/1
• Proj3 out soon, due next Tuesday 8/5
• Will be hand graded in person, signups will
be posted soon
• Midterm regrades due TODAY 7/29
• Proj1 grades out, proj2 hopefully soon
• appeals due 7/31
CS61C L22 Pipelining II, Cache I (27)
Chae, Summer 2008 © UCB
Administrivia
• Lab on polling/interrupts is cancelled
• We will give everyone 4 pts on that lab
• Drop or grading option deadline
• August 1
• summer.berkeley.edu for more details
CS61C L22 Pipelining II, Cache I (28)
Chae, Summer 2008 © UCB
The Big Picture
Computer
Processor Memory
(active) (passive)
(where
Control
programs,
(“brain”)
data live
Datapath when
(“brawn”) running)
CS61C L22 Pipelining II, Cache I (29)
Devices
Input
Output
Keyboard,
Mouse
Disk,
Network
Display,
Printer
Chae, Summer 2008 © UCB
Memory Hierarchy
Storage in computer systems:
• Processor
• holds data in register file (~100 Bytes)
• Registers accessed on nanosecond timescale
• Memory (we’ll call “main memory”)
• More capacity than registers (~Gbytes)
• Access time ~50-100 ns
• Hundreds of clock cycles per memory access?!
• Disk
• HUGE capacity (virtually limitless)
• VERY slow: runs ~milliseconds
CS61C L22 Pipelining II, Cache I (30)
Chae, Summer 2008 © UCB
Motivation: Why We Use Caches (written $)
CPU
µProc
60%/yr.
2000
1999
1998
1996
1995
1994
1993
1992
1991
1988
1987
1986
1985
1984
1983
1982
1981
1980
1
1990
10
1997
Processor-Memory
Performance Gap:
(grows 50% / year)
DRAM
DRAM
7%/yr.
100
1989
Performance
1000
• 1989 first Intel CPU with cache on chip
• 1998 Pentium III has two levels of cache on chip
CS61C L22 Pipelining II, Cache I (31)
Chae, Summer 2008 © UCB
Memory Caching
• Mismatch between processor and
memory speeds leads us to add a new
level: a memory cache
• Implemented with same IC processing
technology as the CPU (usually
integrated on same chip): faster but
more expensive than DRAM memory.
• Cache is a copy of a subset of main
memory.
• Most processors have separate caches
for instructions and data.
CS61C L22 Pipelining II, Cache I (32)
Chae, Summer 2008 © UCB
Memory Hierarchy
Processor
Higher
Levels in
memory
hierarchy
Level 1
Level 2
Increasing
Distance
from Proc.,
Decreasing
speed
Level 3
...
Lower
Level n
Size of memory at each level
As we move to deeper levels the latency
goes up and price per bit goes down.
CS61C L22 Pipelining II, Cache I (33)
Chae, Summer 2008 © UCB
Memory Hierarchy
• If level closer to Processor, it is:
• smaller
• faster
• subset of lower levels (contains most
recently used data)
• Lowest Level (usually disk) contains
all available data (or does it go beyond
the disk?)
• Memory Hierarchy presents the
processor with the illusion of a very
large very fast memory.
CS61C L22 Pipelining II, Cache I (34)
Chae, Summer 2008 © UCB
Memory Hierarchy Analogy: Library (1/2)
• You’re writing a term paper
(Processor) at a table in Doe
• Doe Library is equivalent to disk
• essentially limitless capacity
• very slow to retrieve a book
• Table is main memory
• smaller capacity: means you must return
book when table fills up
• easier and faster to find a book there
once you’ve already retrieved it
CS61C L22 Pipelining II, Cache I (35)
Chae, Summer 2008 © UCB
Memory Hierarchy Analogy: Library (2/2)
• Open books on table are cache
• smaller capacity: can have very few open
books fit on table; again, when table fills up,
you must close a book
• much, much faster to retrieve data
• Illusion created: whole library open on
the tabletop
• Keep as many recently used books open on
table as possible since likely to use again
• Also keep as many books on table as
possible, since faster than going to library
CS61C L22 Pipelining II, Cache I (36)
Chae, Summer 2008 © UCB
Memory Hierarchy Basis
• Cache contains copies of data in
memory that are being used.
• Memory contains copies of data on
disk that are being used.
• Caches work on the principles of
temporal and spatial locality.
• Temporal Locality: if we use it now,
chances are we’ll want to use it again
soon.
• Spatial Locality: if we use a piece of
memory, chances are we’ll use the
neighboring pieces soon.
CS61C L22 Pipelining II, Cache I (37)
Chae, Summer 2008 © UCB
Cache Design
• How do we organize cache?
• Where does each memory address
map to?
(Remember that cache is subset of
memory, so multiple memory addresses
map to the same cache location.)
• How do we know which elements are
in cache?
• How do we quickly locate them?
CS61C L22 Pipelining II, Cache I (38)
Chae, Summer 2008 © UCB
Direct-Mapped Cache (1/4)
• In a direct-mapped cache, each
memory address is associated with
one possible block within the cache
• Therefore, we only need to look in a
single location in the cache for the data if
it exists in the cache
• Block is the unit of transfer between
cache and memory
CS61C L22 Pipelining II, Cache I (39)
Chae, Summer 2008 © UCB
Direct-Mapped Cache (2/4)
Memory
Address Memory
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Cache 4 Byte Direct
Index Mapped Cache
0
1
2
3
Block size = 1 byte
Cache Location 0 can be
occupied by data from:
• Memory location 0, 4, 8, ...
• 4 blocks any memory
location that is multiple of 4
What if we wanted a block
to be bigger than one byte?
CS61C L22 Pipelining II, Cache I (40)
Chae, Summer 2008 © UCB
Direct-Mapped Cache (3/4)
Memory
Memory
Address
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
1C
1E
1
3
5
7
9
0
2
4
6
8
etc
Cache 8 Byte Direct
Index Mapped Cache
0
1
2
3
Block size = 2 bytes
• When we ask for a byte, the
system finds out the right block,
and loads it all!
• How does it know right block?
• How do we select the byte?
• E.g., Mem address 11101?
• How does it know WHICH
colored block it originated from?
• What do you do at baggage claim?
CS61C L22 Pipelining II, Cache I (41)
Chae, Summer 2008 © UCB
Direct-Mapped Cache (4/4)
Memory Address
Memory
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
1C
1E
(addresses shown)
1
3
5
7
9
0
2
4
6
8
etc
0
1
Cache
Index
0
1
2
3
8 Byte Direct
Mapped Cache w/Tag!
8 0
3 0
14 2
1E 3
Tag
Data
(Block size = 2 bytes)
• What should go in the tag?
• Do we need the entire address?
2
- What do all these tags have in
common?
• What did we do with the immediate
when we were branch addressing,
always count by bytes?
3 • Why not count by cache #?
• It’s useful to draw memory with the
Cache# same width as the block size
CS61C L22 Pipelining II, Cache I (42)
Chae, Summer 2008 © UCB
Issues with Direct-Mapped
• Since multiple memory addresses map
to same cache index, how do we tell
which one is in there?
• What if we have a block size > 1 byte?
• Answer: divide memory address into
three fields
ttttttttttttttttt iiiiiiiiii oooo
tag
to check
if have
correct block
CS61C L22 Pipelining II, Cache I (43)
index
to
select
block
byte
offset
within
block
Chae, Summer 2008 © UCB
Direct-Mapped Cache Terminology
• All fields are read as unsigned integers.
• Index: specifies the cache index (which
“row”/block of the cache we should
look in)
• Offset: once we’ve found correct block,
specifies which byte within the block
we want
• Tag: the remaining bits after offset and
index are determined; these are used to
distinguish between all the memory
addresses that map to the same
location
CS61C L22 Pipelining II, Cache I (44)
Chae, Summer 2008 © UCB
TIO Dan’s great cache mnemonic
2(H+W) = 2H * 2W
AREA (cache size, B)
= HEIGHT (# of blocks)
* WIDTH (size of one block, B/block)
Tag Index Offset
HEIGHT
(# of blocks)
CS61C L22 Pipelining II, Cache I (45)
WIDTH
(size of one block, B/block)
AREA
(cache size, B)
Chae, Summer 2008 © UCB
Direct-Mapped Cache Example (1/3)
• Suppose we have a 16KB of data in a
direct-mapped cache with 4 word blocks
• Determine the size of the tag, index and
offset fields if we’re using a 32-bit
architecture
• Offset
• need to specify correct byte within a block
• block contains 4 words
= 16 bytes
= 24 bytes
• need 4 bits to specify correct byte
CS61C L22 Pipelining II, Cache I (46)
Chae, Summer 2008 © UCB
Direct-Mapped Cache Example (2/3)
• Index: (~index into an “array of blocks”)
• need to specify correct block in cache
• cache contains 16 KB = 214 bytes
• block contains 24 bytes (4 words)
• # blocks/cache
=
=
=
bytes/cache
bytes/block
214 bytes/cache
24 bytes/block
210 blocks/cache
• need 10 bits to specify this many blocks
CS61C L22 Pipelining II, Cache I (47)
Chae, Summer 2008 © UCB
Direct-Mapped Cache Example (3/3)
• Tag: use remaining bits as tag
• tag length = addr length – offset - index
= 32 - 4 - 10 bits
= 18 bits
• so tag is leftmost 18 bits of memory address
• Why not full 32 bit address as tag?
• All bytes within block need same address (4b)
• Index must be same for every address within
a block, so it’s redundant in tag check, thus
can leave off to save memory (here 10 bits)
CS61C L22 Pipelining II, Cache I (48)
Chae, Summer 2008 © UCB
Caching Terminology
• When we try to read memory,
3 things can happen:
1. cache hit:
cache block is valid and contains
proper address, so read desired word
2. cache miss:
nothing in cache in appropriate block,
so fetch from memory
3. cache miss, block replacement:
wrong data is in cache at appropriate
block, so discard it and fetch desired
data from memory (cache always copy)
CS61C L22 Pipelining II, Cache I (49)
Chae, Summer 2008 © UCB
Peer instruction
• Consider an address split into fields for cache
access as follows:
ttttttttttttttttttttttt iiiiii oooo
• How big are the cache blocks in words?
4
8
16
32
• How many entries does the cache have?
4
8
16
32
• How big is a cache entry?
24
33
55
56
CS61C L22 Pipelining II, Cache I (50)
Chae, Summer 2008 © UCB
In Conclusion
• Pipeline challenge is hazards
• Forwarding helps w/many data hazards
• Delayed branch helps with control hazard in
5 stage pipeline
• Load delay slot / interlock necessary
• More aggressive performance:
• Superscalar
• Out-of-order execution
• Use caches to simulate fast large
memory
CS61C L22 Pipelining II, Cache I (51)
Chae, Summer 2008 © UCB