inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture #18 – Combinational Logic Blocks,
Latches
2008-7-22
Albert Chae, Instructor
CS61C L18 Combinational Logic Blocks, Latches (1)
Chae, Summer 2008 © UCB
Review
• Use this table and techniques we
learned to transform from 1 to another
CS61C L18 Combinational Logic Blocks, Latches (2)
Chae, Summer 2008 © UCB
Today
• Common Combinational Logic Blocks
• Data Multiplexors
• Arithmetic and Logic Unit
• Adder/Subtractor
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Chae, Summer 2008 © UCB
Data Multiplexor (here 2-to-1, n-bit-wide)
“mux”
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N instances of 1-bit-wide mux
How many rows in TT?
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How do we build a 1-bit-wide mux?
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4-to-1 Multiplexor?
How many rows in TT?
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Is there any other way to do it?
Hint: March Madness
Ans: Hierarchically!
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Do you really understand NORs?
• If one input is 1, what is a NOR?
• If one input is 0, what is a NOR?
A
A B NOR
0 0 1
B
_
0 1 0
BP 0
1 0 0
C
NOR
1 1 0
0Q 1
AD
CS61C L18 Combinational Logic Blocks, Latches (9)
NOR
D
C
A NOR
0 P
B’
1 Q
0
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Do you really understand NANDs?
• If one input is 1, what is a NAND?
• If one input is 0, what is a NAND?
A
A B NAND
NAND
0 0 1
B
0 1 1
1P 0
1 0 1
C
NAND
_
1 1 0
BQ 1
NAND
AD
CS61C L18 Combinational Logic Blocks, Latches (10)
A
D
0
1
C
1
P
B’
Q
Chae, Summer 2008 © UCB
Arithmetic and Logic Unit
• Most processors contain a special
logic block called “Arithmetic and
Logic Unit” (ALU)
• We’ll show you an easy one that does
ADD, SUB, bitwise AND, bitwise OR
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Chae, Summer 2008 © UCB
Our simple ALU
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Adder/Subtracter Design -- how?
• Truth-table, then
determine canonical
form, then minimize
and implement as
we’ve seen before
CS61C L18 Combinational Logic Blocks, Latches (13)
• Look at breaking the
problem down into
smaller pieces that
we can cascade or
hierarchically layer
Chae, Summer 2008 © UCB
Adder/Subtracter – One-bit adder LSB…
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Adder/Subtracter – One-bit adder (1/2)…
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Adder/Subtracter – One-bit adder (2/2)…
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Administrivia
• HW4 Due Friday 7/25
• Learn Logisim in the next few labs
• Proj3 poll?
• Complaints about HW1 and 2
• Submit by Friday or we won’t look at it
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N 1-bit adders  1 N-bit adder
b0
+
+
+
What about overflow?
Overflow = cn?
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Chae, Summer 2008 © UCB
What about overflow?
• Consider a 2-bit signed # & overflow:
•10
•11
•00
•01
= -2 + -2 or -1
= -1 + -2 only
= 0 NOTHING!
= 1 + 1 only
• Highest adder
±
#
• C1 = Carry-in = Cin, C2 = Carry-out = Cout
• No Cout or Cin  NO overflow!
• Cin, and Cout  NO overflow!
What
•
C
,
but
no
C

A,B
both
>
0,
overflow!
in
out
op?
• Cout, but no Cin  A,B both < 0, overflow!
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Chae, Summer 2008 © UCB
What about overflow?
• Consider a 2-bit signed # & overflow:
10
11
00
01
= -2 + -2 or -1
= -1 + -2 only
= 0 NOTHING!
= 1 + 1 only
±
#
• Overflows when…
• Cin, but no Cout  A,B both > 0, overflow!
• Cout, but no Cin  A,B both < 0, overflow!
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Extremely Clever Subtractor
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Taking advantage of sum-of-products
• Since sum-of-products is a convenient
notation and way to think about
design, offer hardware building blocks
that match that notation
• One example is
Programmable Logic Arrays (PLAs)
• Designed so that can select (program)
ands, ors, complements after you get
the chip
• Late in design process, fix errors, figure
out what to do later, …
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Programmable Logic Arrays
• Pre-fabricated building block of many
AND/OR gates
• “Programmed” or “Personalized" by making or
breaking connections among gates
• Programmable array block diagram for sum of
products form
Or Programming:
• How to combine product terms?
• How many outputs?
• • •
inputs
AND
array
product
terms
And Programming:
• How many inputs?
• How to combine inputs?
• How many product terms?
CS61C L18 Combinational Logic Blocks, Latches (23)
OR
array
outputs
• • •
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Enabling Concept
• Shared product terms among outputs
F0
F1
F2
F3
example:
=
=
=
=
A
+
A C' +
B' C' +
B' C +
1 = uncomplemented in term
0 = complemented in term
– = does not participate
personality matrix
Product
term
AB
B'C
AC'
B'C'
A
inputs
A B
1 1
– 0
1 –
– 0
1 –
C
–
1
0
0
–
outputs
F0 F1 F2
0 1 1
0 0 0
0 1 0
1 0 1
1 0 0
B' C'
AB
AB
A input side: 3 inputs
F3
0
1
0
0
1
CS61C L18 Combinational Logic Blocks, Latches (24)
output side: 4 outputs
1 = term connected to output
0 = no connection to output
reuse of terms;
5 product terms
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Before Programming
• All possible connections available before
“programming”
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After Programming
• Unwanted connections are "blown"
• Fuse (normally connected, break unwanted
ones)
• Anti-fuse (normally disconnected, make wanted
connections)
A
B
C
AB
B'C
AC'
B'C'
A
F0
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F1
F2
F3
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Alternate Representation
• Short-hand notation--don't have to draw all
the wires
• X Signifies a connection is present and
perpendicular signal is an input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
A B C D
AB
A'B'
CD'
C'D
AB+A'B'
CD'+C'D
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Chae, Summer 2008 © UCB
Peer Instruction
A. Truth table for mux with 4-bits of
select signal has 24 rows
B. We could cascade N 1-bit shifters
to make 1 N-bit shifter for sll, srl
C. If 1-bit adder delay is T, the N-bit
adder delay would also be T
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0:
1:
2:
3:
4:
5:
6:
7:
ABC
FFF
FFT
FTF
FTT
TFF
TFT
TTF
TTT
Chae, Summer 2008 © UCB
Peer Instruction Answer
A. Truth table for mux with 4-bits of signals
controls 16 inputs, for a total of 20 inputs,
so truth table is 220 rows…FALSE
B. We could cascade N 1-bit shifters to
make 1 N-bit shifter for sll, srl … TRUE
C. What about the cascading carry? FALSE
ABC
A. Truth table for mux with 4-bits of
0: FFF
4
signals is 2 rows long
1: FFT
B. We could cascade N 1-bit shifters
to make 1 N-bit shifter for sll, srl
C. If 1-bit adder delay is T, the N-bit
adder delay would also be T
CS61C L18 Combinational Logic Blocks, Latches (29)
2:
3:
4:
5:
6:
7:
FTF
FTT
TFF
TFT
TTF
TTT
Chae, Summer 2008 © UCB
Combinational Logic from 10 miles up
• CL circuits simply compute a binary
function (e.g., from truthtable)
• Once the inputs go away, the outputs
go away, nothing is saved, no STATE
• Similar to a function in Scheme with no
set! or define to save anything
X
Y
X
Y
(define (xor x y)
Z
(or (and (not x) y)
(and x (not y))))
• How does the computer remember
data? [e.g., for registers]
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State Circuits Overview
• State circuits have feedback, e.g.
in0
in1
Combilab
12
national
counter
Logic
out0
out1
• Output is function of
inputs + fed-back signals.
• Feedback signals are the circuit's state.
• What aspects of this circuit might cause
complications?
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A simpler state circuit: two inverters
0
1! 0
1
0
• When started up, it's internally stable.
• Provide an or gate for coordination:
1
0
1
0
0
1
10
1
0
• What's the result? How do we set to 0?
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Chae, Summer 2008 © UCB
An R-S latch (cross-coupled NOR gates)
• S means “set” (to 1),
R means “reset” (to 0).
0
1
0
1
1
0
1
0
_
Q
1
0
00
1
A
0
0
1
1
B
0
1
0
1
NOR
1
0
0
0
Hold!
0
1
• Adding Q’ gives standard RS-latch:
Truth table
S R Q
0 0 hold (keep value)
0 1 0
1 0 1
1 1 unstable
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Chae, Summer 2008 © UCB
An R-S latch (in detail)
Truth table
A
0
0
1
1
B
0
1
0
1
NOR
1
0
0
0
_
S R Q Q Q(t+t)
0 0 0 1 0 hold
0 0 1 0 1 hold
0 1 0 1 0
reset
0 1 1 0 0
reset
1 0 0 1 1 set
1 0 1 0 1 set
1 1 0 x x
unstable
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Chae, Summer 2008 © UCB
Controlling R-S latch with a clock
• Can't change R and S while clock is
active.
A
0
0
1
1
B
0
1
0
1
NOR
R'
1
0 clock'
0
S'
0
R
Q
Q'
S
• Clocked latches are called flip-flops.
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D flip-flop are what we really use
• Inputs C (clock) and D.
• When C is 1, latch open, output = D
(even if it changes, “transparent latch”)
• When C is 0, latch closed,
output = stored value.
C
0
0
1
1
D
0
1
0
1
AND
0
0
0
1
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Chae, Summer 2008 © UCB
D flip-flop details
• We don’t like transparent latches
• We can build them so that the latch is
only open for an instant, on the rising
edge of a clock (as it goes from 01)
D
C
Q
Timing Diagram
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“And In conclusion…”
• Use muxes to select among input
• S input bits selects 2S inputs
• Each input can be n-bits wide, indep of S
• Can implement muxes hierarchically
• ALU can be implemented using a mux
• Coupled with basic block elements
• N-bit adder-subtractor done using N 1bit adders with XOR gates on input
• XOR serves as conditional inverter
• Latches are used to implement flipflops
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Chae, Summer 2008 © UCB