inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture #15 – Intro to Synchronous Digital
Systems, State Elements I
2008-7-16
Go BEARS~
Albert Chae, Instructor
CS61C L15 Intro to SDS, State Elements I (1)
Chae, Summer 2008 © UCB
What are “Machine Structures”?
Application (Netscape)
Compiler
Software
Hardware
Assembler
Operating
System
(MacOS X)
Processor Memory I/O system
61C
Instruction Set
Architecture
Datapath & Control
Digital Design
Circuit Design
transistors
Coordination of many levels of abstraction
ISA is an important abstraction level:
contract between HW & SW
CS61C L15 Intro to SDS, State Elements I (2)
Chae, Summer 2008 © UCB
Below the Program
• High-level language program (in C)
swap
int v[], int k){
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
C compiler
}
• Assembly language program (for MIPS)
swap: sll $2, $5, 2
add
$2, $4,$2
lw
$15, 0($2)
lw
$16, 4($2)
sw
$16, 0($2)
sw
$15, 4($2)
jr
$31
assembler
• Machine (object) code (for MIPS)
000000 00000 00101 0001000010000000
000000 00100 00010 0001000000100000 . . .
CS61C L15 Intro to SDS, State Elements I (3)
Chae, Summer 2008 © UCB
61C Levels of Representation
High Level Language
Program (e.g., C)
Compiler
Assembly Language
Program (e.g.,MIPS)
Assembler
Machine Language
Program (MIPS)
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw
lw
sw
sw
0000
1010
1100
0101
$t0, 0($2)
$t1, 4($2)
$t1, 0($2)
$t0, 4($2)
1001
1111
0110
1000
1100
0101
1010
0000
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine
Interpretation
Hardware Architecture Description
(Logic, Logisim, etc.)
Architecture
Implementation
Logic Circuit Description
(Logisim, etc.)
CS61C L15 Intro to SDS, State Elements I (4)
Chae, Summer 2008 © UCB
Synchronous Digital Systems
The hardware of a processor, such as the MIPS, is an
example of a Synchronous Digital System
Synchronous:
• Means all operations are coordinated by
a central clock.
- It keeps the “heartbeat” of the system!
Digital:
• Mean all values are represented by
discrete values
• Electrical signals are treated as 1’s and
0’s and grouped together to form words.
CS61C L15 Intro to SDS, State Elements I (5)
Chae, Summer 2008 © UCB
Logic Design
• Next 4 weeks: we’ll study how a modern
processor is built; starting with basic
elements as building blocks.
• Why study hardware design?
• Understand capabilities and limitations of
hardware in general and processors in
particular.
• What processors can do fast and what they
can’t do fast (avoid slow things if you want your
code to run fast!)
• Background for more detailed hardware courses
(CS 150, CS 152, EE 192)
• There is just so much you can do with
processors. At some point you may need to
design your own custom hardware.
CS61C L15 Intro to SDS, State Elements I (6)
Chae, Summer 2008 © UCB
PowerPC Die Photograph
Let’s look
closer…
CS61C L15 Intro to SDS, State Elements I (7)
Chae, Summer 2008 © UCB
Transistors 101
• MOSFET
• Metal-Oxide-Semiconductor
Field-Effect Transistor
G
• Come in two types:
-
n-type NMOSFET
p-type PMOSFET
• For n-type (p-type opposite)
S
D
G
S
n-type
• If voltage not enough between G & S,
transistor turns “off” (cut-off)
and Drain-Source NOT connected
• If the G & S voltage is high enough,
transistor turns “on” (saturation)
and Drain-Source ARE connected
D
p-type
Side view
www.wikipedia.org/wiki/Mosfet
CS61C L15 Intro to SDS, State Elements I (8)
Chae, Summer 2008 © UCB
Transistor Circuit Rep. vs. Block diagram
• Chips is composed of nothing but
transistors and wires.
• Small groups of transistors form useful
building blocks.
“1” (voltage source)
a
0
0
1
1
b
0
1
0
1
c
1
1
1
0
“0” (ground)
• Block are organized in a hierarchy to build
higher-level blocks: ex: adders.
CS61C L15 Intro to SDS, State Elements I (9)
Chae, Summer 2008 © UCB
Signals and Waveforms: Clocks
• Signals
• When digital is only treated as 1 or 0
• Is transmitted over wires continuously
• Transmission is effectively instant
- Implies that any wire only contains 1 value
at a time
CS61C L15 Intro to SDS, State Elements I (10)
Chae, Summer 2008 © UCB
Signals and Waveforms
CS61C L15 Intro to SDS, State Elements I (11)
Chae, Summer 2008 © UCB
Signals and Waveforms: Grouping
CS61C L15 Intro to SDS, State Elements I (12)
Chae, Summer 2008 © UCB
Signals and Waveforms: Circuit Delay
2
3
4
5
3
4
5
6
5
7
CS61C L15 Intro to SDS, State Elements I (13)
9
11
Chae, Summer 2008 © UCB
Type of Circuits
• Synchronous Digital Systems are made
up of two basic types of circuits:
• Combinational Logic (CL) circuits
• Our previous adder circuit is an example.
• Output is a function of the inputs only.
• Similar to a pure function in mathematics,
y = f(x). (No way to store information from
one invocation to the next. No side
effects)
• State Elements: circuits that store
information.
CS61C L15 Intro to SDS, State Elements I (14)
Chae, Summer 2008 © UCB
Circuits with STATE (e.g., register)
CS61C L15 Intro to SDS, State Elements I (15)
Chae, Summer 2008 © UCB
Peer Instruction
A. SW can peek at HW (past ISA
abstraction boundary) for optimizations
B. SW can depend on particular HW
implementation of ISA
0:
1:
2:
3:
C. Timing diagrams serve as a critical
debugging tool in the EE toolkit
CS61C L15 Intro to SDS, State Elements I (16)
AB
FF
FT
TF
TT
White
is
true
C: T F
Chae, Summer 2008 © UCB
Sample Debugging Waveform
CS61C L15 Intro to SDS, State Elements I (17)
Chae, Summer 2008 © UCB
Administrivia
• Hw3 is due today
• Proj2 is due Friday
• Faux midterm today 6-9
• Review session Thursday in lecture
• Extra MT OH?
• Midterm 7/21 7-10p in 155 Dwinelle
CS61C L15 Intro to SDS, State Elements I (18)
Chae, Summer 2008 © UCB
Uses for State Elements
1. As a place to store values for some
indeterminate amount of time:
•
Register files (like $1-$31 on the MIPS)
•
Memory (caches, and main memory)
2. Help control the flow of information
between combinational logic blocks.
•
State elements are used to hold up the
movement of information at the inputs
to combinational logic blocks and
allow for orderly passage.
CS61C L15 Intro to SDS, State Elements I (19)
Chae, Summer 2008 © UCB
Accumulator Example
Why do we need to control the flow of information?
S=0;
for (i=0;i<n;i++)
S = S + Xi
Assume:
Want:
• Each X value is applied in succession,
one per cycle.
• After n cycles the sum is present on S.
CS61C L15 Intro to SDS, State Elements I (20)
Chae, Summer 2008 © UCB
First try…Does this work?
Feedback
Nope!
Reason #1… What is there to control the
next iteration of the ‘for’ loop?
Reason #2… How do we say: ‘S=0’?
CS61C L15 Intro to SDS, State Elements I (21)
Chae, Summer 2008 © UCB
Second try…How about this?
Rough
timing…
Register is used to hold up the transfer of data to adder.
CS61C L15 Intro to SDS, State Elements I (22)
Chae, Summer 2008 © UCB
Register Details…What’s inside?
• n instances of a “Flip-Flop”
• Flip-flop name because the output flips and
flops between and 0,1
• D is “data”, Q is “output”
• Also called “d-type Flip-Flop”
CS61C L15 Intro to SDS, State Elements I (23)
Chae, Summer 2008 © UCB
What’s the timing of a Flip-flop? (1/2)
• Edge-triggered d-type flip-flop
• This one is “positive edge-triggered”
• “On the rising edge of the clock, the input d
is sampled and transferred to the output. At
all other times, the input d is ignored.”
• Example waveforms:
CS61C L15 Intro to SDS, State Elements I (24)
Chae, Summer 2008 © UCB
What’s the timing of a Flip-flop? (2/2)
• Edge-triggered d-type flip-flop
• This one is “positive edge-triggered”
• “On the rising edge of the clock, the input d
is sampled and transferred to the output. At
all other times, the input d is ignored.”
• Example waveforms (more detail):
CS61C L15 Intro to SDS, State Elements I (25)
Chae, Summer 2008 © UCB
Accumulator Revisited (proper timing 1/2)
• Reset input to register is
used to force it to all
zeros (takes priority over
D input).
• Si-1 holds the result of the
ith-1 iteration.
• Analyze circuit timing
starting at the output of
the register.
CS61C L15 Intro to SDS, State Elements I (26)
Chae, Summer 2008 © UCB
Accumulator Revisited (proper timing 2/2)
• reset signal shown.
• Also, in practice X might
not arrive to the adder at
the same time as Si-1
• Si temporarily is wrong,
but register always
captures correct value.
• In good circuits,
instability never happens
around rising edge of clk.
CS61C L15 Intro to SDS, State Elements I (27)
Chae, Summer 2008 © UCB
Recap of Timing Terms
• Clock (CLK) - steady square wave that
synchronizes system
• Setup Time - when the input must be stable before
the rising edge of the CLK
• Hold Time - when the input must be stable after the
rising edge of the CLK
• “CLK-to-Q” Delay - how long it takes the output to
change, measured from the rising edge
• Flip-flop - one bit of state that samples every rising
edge of the CLK
• Register - several bits of state that samples on
rising edge of CLK or on LOAD
CS61C L15 Intro to SDS, State Elements I (28)
Chae, Summer 2008 © UCB
Finite State Machines (FSM) Introduction
• You have seen FSMs
in other classes.
• Same basic idea.
• The function can be
represented with a
“state transition
diagram”.
• With combinational
logic and registers,
any FSM can be
implemented in
hardware.
CS61C L15 Intro to SDS, State Elements I (29)
Chae, Summer 2008 © UCB
Finite State Machine Example: 3 ones…
FSM to detect the occurrence of 3 consecutive 1’s in the input.
Draw the FSM…
Assume state transitions are controlled by the clock:
on each clock cycle the machine checks the inputs and moves
to a new state and produces a new output…
CS61C L15 Intro to SDS, State Elements I (30)
Chae, Summer 2008 © UCB
Hardware Implementation of FSM
… Therefore a register is needed to hold the a representation of which
state the machine is in. Use a unique bit pattern for each state.
+
=
?
Combinational logic circuit is
used to implement a function
maps from present state and
input to next state and output.
CS61C L15 Intro to SDS, State Elements I (31)
Chae, Summer 2008 © UCB
Hardware for FSM: Combinational Logic
Next lecture we will discuss the detailed implementation,
but for now can look at its functional specification,
truth table form.
Truth table…
PS Input
00
0
00
1
01
0
01
1
10
0
10
1
CS61C L15 Intro to SDS, State Elements I (32)
NS
00
01
00
10
00
00
Output
0
0
0
0
0
1
Chae, Summer 2008 © UCB
Peer Instruction
A. HW feedback akin to SW recursion
B. The minimum period of a usable
synchronous circuit is at least the
CLK-to-Q delay
C. You can build a FSM to signal
when an equal number of 0s and
1s has appeared in the input.
CS61C L15 Intro to SDS, State Elements I (33)
AB
0: FF
1: FT
2: TF
3: TT
White
is
true
C: T F
Chae, Summer 2008 © UCB
Conclusion
• ISA is very important abstraction layer
• Contract between HW and SW
• Clocks control pulse of our circuits
• Voltages are analog, quantized to 0/1
• Circuit delays are fact of life
• Two types of circuits:
• Stateless Combinational Logic (&,|,~)
• State circuits (e.g., registers)
CS61C L15 Intro to SDS, State Elements I (35)
Chae, Summer 2008 © UCB
“And In conclusion…”
• State elements are used to:
• Build memories
• Control the flow of information between other state
elements and combinational logic
• D-flip-flops used to build registers
• Clocks tell us when D-flip-flops change
• Setup and Hold times important
• Finite State Machines extremely useful
• You’ll see them again (150,152), 164, 172, 174, etc
CS61C L15 Intro to SDS, State Elements I (36)
Chae, Summer 2008 © UCB