EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
EECS 40 Spring 2003
Lecture 23
4/1/03
Computing Gate Delay
Prof. Andy Neureuther
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Discharging Capacitance through a MOS device?
Equivalent resistance model for MOS
CMOS Logic operation
Path dependent delay
Worst cae and Cascade
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Transient Gate Problem: Discharging and
Charging Capacitance on the Output
VDD
VIN-U
IOUT
p-type MOS
Transistor
(PMOS)
Output
5V => 0
VIN = VDD = 5V
VIN-D
n-type MOS
Transistor
VOUT
(NMOS)
Copyright 2001, Regents of University of California
COUT = 50 fF
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Output Propagation Delay High to Low
VOUT(0) = 5V
IOUT-SAT-D
= 100 mA
VIN = 5V
100
IOUT(mA)
60
COUT = 50 fF 2
0
IOUT-SAT-D = 100 mA
0
V3OUT(V) 5
When VIN goes High VOUT starts decreases with time
Assume that the necessary voltage swing to cause the next
downstream gate to begin to switch is VDD/2 or 2.5V.
That is the propagation delay tHL for the output to go from
high to low is the time to go from VDD = 5V to to VDD/2 =2.5V
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Output Propagation Delay High to Low (Cont.)
VOUT(0) = 5V
IOUT-SAT-D
= 100 mA
VIN = 5V
100
IOUT(mA)
60
COUT = 50 fF 2
0
IOUT-SAT-D = 100 mA
0
V3OUT(V) 5
When VOUT > VOUT-SAT-D the available current is IOUT-SAT-D
For this circuit when VOUT > VOUT-SAT-D the available current
is constant at IOUT-SAT-D and the capacitor discharges.
The propagation delay is thus
COUT V
COUTVDD
50 fF  2.5V
t 


 1.25 ns
I OUT  SAT  D 2 I OUT  SAT  D
100 mA
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Switched Equivalent Resistance Model
The above model assumes the device is an ideal constant current source.
1) This is not true below VOUT-SAT-D and leads to in accuracies.
2) Combining ideal current sources in networks with series
and parallel connections is problematic.
Instead define an equivalent resistance for the device by setting 0.69RDC
equal to the t found above
This gives
RD 
COUTVDD
t 
 0.69 RD COUT
2 I OUT  SAT  D
VDD
VDD
3
3 5V


 37 .5k
2  0.69 I OUT  SAT  D 4 I OUT  SAT  D 4 100 mA
Each device can now be replaced by this equivalent resistor.
Copyright 2001, Regents of University of California
RD
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
¾ VDD/ISAT Physical Interpretation
VOUT(0) = 5V
IOUT-SAT-D
= 100 mA
VIN = 5V
100
IOUT(mA)
60
COUT = 50 fF 2
0
IOUT-SAT-D = 100 mA
0
V3OUT(V) 5
¾ VDD is the average value of VOUT
Approximate the NMOS device curve by a straight line
from (0,0) to (IOUT-SAT-D, ¾ VDD ).
Interpret the straight line as a resistor with
1/(slope) = R = ¾ VDD/ISAT
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Switched Equivalent Resistance Values
The resistor values depend on the properties of silicon,
geometrical layout, design style and technology node.
n-type silicon has a carrier mobility that is 2 to 3 times
higher than p-type.
The resistance is inversely proportion to the gate
width/length in the geometrical layout.
Design styles may restrict all NMOS and PMOS to be of a
predetermined fixed size.
The current per unit width of the gate increases nearly
inversely with the linewidth.
For convenience in EE 42 we assume RD = RU = 10 k
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Inverter Propagation Delay
Discharge (pull-down)
VDD
VDD
VOUT
VIN =
Vdd
COUT = 50fF
VOUT
VIN =
Vdd
RD
t = 0.69RDCOUT = 0.69(10k)(50fF) = 345 ps
Discharge (pull-up)
t = 0.69RUCOUT = 0.69(10k)(50fF) = 345 ps
Copyright 2001, Regents of University of California
COUT = 50fF
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
NMOS and
PMOS use the
same set of
input signals
CMOS Logic Gate
VDD
PMOS only in pull-up
PMOS conduct when input is low
A
B
PMOS do not conduct when
A +(BC)
C
VOUT
NMOS only in pull-down
B
NMOS conduct when input is high.
A
NMOS conduct for A + (BC)
C
Logic is Complementary and
produces F = A + (BC)
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
CMOS Logic Gate: Example Inputs
VDD
A=0
PMOS all conduct
A
B=0
Output is High
C=0
B
C
VOUT
B
= VDD
NMOS do not conduct
A
C
Logic is Complementary and
produces F = 1
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
CMOS Logic Gate: Example Inputs
VDD
A=0
PMOS A conducts; B and C Open
A
B=1
Output is Low
C=1
B
C
=0
VOUT
B
NMOS B and C conduct; A open
A
C
Logic is Complementary and
produces F = 0
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Switched Equivalent Resistance Network
VDD
VDD
RU
A
A
RU
RU
B
C
VOUT
C
B
Switches
close when
input is low.
VOUT
RD
B
A
RD
B
A
RD
C
C
Copyright 2001, Regents of University of California
Switches
close when
input is high.
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Logic Gate Propagation Delay: Initial State
VDD
The initial state depends on the old (previous) inputs.
RU
A
RU
RU
C
B
VOUT
RD
RD
B
A
RD
Example: A=0, B=0, C=0 for a long
time.
These inputs provided a path to VDD
for a long time and the capacitor has
precharged up to VDD = 5V.
COUT = 50 fF
C
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Logic Gate Propagation Delay: Transient
VDD
RU
A
RU
C
B
The equivalent resistance of the pull-down or pullup network for the transient phase depends on the
new present input state.
Example: At t=0, B and C switch from
low to high (VDD) and A remains low.
RU
This breaks the path from VOUT to VDD
VOUT
RD
RD
B
A
RD
And opens a path from VOUT to GND
COUT discharges through the pull-down
resistance of gates B and C in series.
COUT = 50 fF t = 0.69(RDB+RDC)COUT
= 0.69(20k)(50fF) = 690 ps
C
The propagation delay is two
times longer than that for the
inverter!
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Logic Gate: Worst Case Scenarios
VDD
What combination of previous and
present logic inputs will make the
Pull-Up the fastest?
RU
A
RU
RU
C
B
VOUT
RD
RD
B
A
RD
C
What combination of previous and
present logic inputs will make the
Pull-Up the slowest?
What combination of previous and
present logic inputs will make the
Pull-Down the fastest?
COUT = 50 fF
What combination of previous and
present logic inputs will make the
Pull-Down the slowest?
Copyright 2001, Regents of University of California
Fastest
overall?
Slowest
overall?
EECS 42 Intro. electronics for CS Spring 2003
Lecture 18: 04/0703 A.R. Neureuther
Version Date 04/03/03
Logic Gate Cascade
To avoid large resistance due to many gates in series, logic functions with 4 or
more inputs are usually made from cascading two or more 2-4 input blocks.
VDD
B2 = VOUT 1
A1
VDD
A2
B1
VOUT 1 B2
C2
B2
A1
The four independent
input are A1, B1, A2
and C2.
B1
A2
50 fF
C2
Copyright 2001, Regents of University of California
VOUT 2
Fastest: A2 high
discharges gate 2
without even waiting
for the output of gate 1.
Slowest: C2 high
and A2 low makes
gate 2 wait for Gate
50 fF
1 output