EECS150 - Digital Design
Lecture 14 - Sequential Circuits I
(State Elements)
March 12, 2002
John Wawrzynek
Spring 2002
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Sequential Circuits
Circuit with feedback.
• Examples:
• Sequential circuits exhibit either
synchronous or asynchronous
behavior:
FSM
– Synchronous: “state” of the
circuit changes at regular
intervals controlled by a clock.
– Asynchronous: state changes
with changing inputs. No clock
present or circuit doesn’t wait
for it.
D-type latch
How about CL logic with feedback
but without register?
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Cross-coupled NOR gates
remember,
R
S
• If both R=0 & S=0, then cross-couped NORs
equivalent to a stable latch:
NOR
00 1
01 0
10 0
11 0
• What happens if R or S or both become = 1?
0
R
S
0 1 0
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Q 0 1
Q' 1 0
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Asynchronous State Transition Diagram
SR=00
SR=01
SR=00
SR=10
SR=10
QQ'
01
SR=01
SR=11
SR=01
QQ'
10
SR=11
QQ'
00
SR=10
SR=00
?
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SR Latch:
SR
00
01
10
11
Q
hold
0
1
indeterminate
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Nand-gate based SR latch
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Level-sensitive SR Latch
• The input “C” works as an “enable” signal, latch only changes output
when C is high.
• usually connected to clock.
• Generally, it is not a good idea to use a clock as a logic signal (into
gates etc.). This is a special case.
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D-latch
Compare to transistor version:
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Flip-flops
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J-K FF
• Add logic to eliminate
“indeterminate” action of
RS FF.
• New action is “toggle”
• J = “jam”
• K = “kill”
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JK
00
00
01
01
10
10
11
11
Q(t) Q(t+D)
0
0
hold
1
1
0
0
reset
1
0
0
1
set
1
1
0
1
toggle
1
0
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J-K Flip-flop from D-FF
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Toggle Flip-flop from D-FF
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Storage Element Taxonomy
synchronous
asynchronous
level-sensitive edge-triggered
D-type
JK-type
RS-type
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n.a.
n.a.
“latch”
n.a.
“flip-flop”
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“latch”
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Design Example with RS FF
• With D-type FF state elements, new state iscomputed
based on inputs & present state bits - reloaded each cycle.
• With RS (or JK) FF state elements, inputs are used to
determine conditions under which to set or reset state bits.
• Example: bit-serial adder (LSB first)
n-bit shift registers
A
B
With D-FF for carry
reset
FF
FA
c s
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n-bit shift register
R
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Bit-serial adder with RS FF
• RS FF stores the carry:
a b ci ci+1
000
0
001
0
010
0
011
1
100
0
101
1
110
1
111
1
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s
0 Carry kill a’b’
1
1
a
0
1
b
0
0 Carry generate
ab
1
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S
R
Q
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Resets/presets
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Adding Reset/Presets
• D-type flip-flop from latches:
D-latch circuit
• Asynchronous reset in Flip-flop:
Either inverter (or both) can be replaced by either NOR gate or NAND gate in
the second latch of the flip-flop. The second input to the gate is connected
to reset or preset signal. The choice of NOR versus NAND defines the
sense of the reset/preset (active-high versus active-low). The choice which
inverter to replace defines reset versus preset.
• Synchronous reset:
A similar procedure as above is applied to the first latch of the flip-flop.
Additional logic is needed to synchronize the reset signal with the correct
level of the clock.
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