EECS150 - Digital Design
Lecture 7 - Boolean Algebra II
February 12, 2002
John Wawrzynek
Spring 2002
EECS150 - Lec7-Bool2
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Outline
• Canonical Forms
– They give us a method to go from TT to Boolean Equations
• Two-level Logic Simplification
– K-map method
• Multi-level Logic
• NAND/NOR networks
• EXOR revisited
Spring 2002
EECS150 - Lec7-Bool2
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Canonical Forms
• Standard form for a Boolean expression - unique algebraic
expression from a TT.
• Two Types:
* Sum of Products (SOP)
* Product of Sums (POS)
• Sum of Products (disjunctive normal form, minterm expansion).
Example:
minterms
a’b’c’
a’b’c
a’bc’
a’bc
ab’c’
ab’c
abc’
abc
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abc
000
001
010
011
100
101
110
111
f f’
01
01
01
10
10
10
10
10
One product (and) term for each 1 in f:
f = a’bc + ab’c’ + ab’c +abc’ +abc
f’ = a’b’c’ + a’b’c + a’bc’
EECS150 - Lec7-Bool2
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Sum of Products (cont.)
Canonical Forms are usually not minimal:
Our Example:
f = a’bc + ab’c’ + ab’c + abc’ +abc
= a’bc + ab’ + ab
= a’bc + a
(x’y + x = y + x)
= a + bc
f’ = a’b’c’ + a’b’c + a’bc’
= a’b’ + a’bc’
= a’ ( b’ + bc’ )
= a’ ( b’ + c’ )
= a’b’ + a’c’
Spring 2002
EECS150 - Lec7-Bool2
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Canonical Forms
• Product of Sums (conjunctive normal form, maxterm expansion).
Example:
maxterms
a+b+c
a+b+c’
a+b’+c
a+b’+c’
a’+b+c
a’+b+c’
a’+b’+c
a’+b’+c’
abc
000
001
010
011
100
101
110
111
f f’
01
01
01
10
10
10
10
10
One sum (or) term for each 0 in f:
f = (a+b+c)(a+b+c’)(a+b’+c)
f’ = (a+b’+c’)(a’+b+c)(a’+b+c’)(a’+b’+c)(a+b+c’)
Mapping from SOP to POS (or POS to SOP): Derive TT then proceed.
Spring 2002
EECS150 - Lec7-Bool2
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Two-level Logic Simplication
Key tool: The Uniting Theorem
x (y’ + y) = x (1) = x
ab
00
01
10
11
f
0
0
1
1
ab
00
01
10
11
g
1
0
1
0
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f = ab’ + ab = a(b’+b) = a
b values change within
the on-set rows
a values don’t change
b is eliminated, a remains
g = a’b’+ab’ = (a’+a)b’ =b’
b values stay the same
a values changes
b’ remains, a eliminated
EECS150 - Lec7-Bool2
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Boolean Cubes
Visual technique for identifying when the Uniting Theorem
can be applied
2-cube
3-cube
1-cube
01
0
011
111
010
1
x
11
xy
00
110
y
001
000
x
10
101
z
100
• Sub-cubes of on nodes can be used for simplification.
– On-set - filled in nodes, off-set - empty nodes
ab
00
01
10
11
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f
0
0
1
1
g
1
0
1
0
01
b
11
a asserted & unchanged
b varies
f
ab + ab' = a
00
a
10
EECS150 - Lec7-Bool2
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3-variable cube example
(a' + a)bc
FA carry out:
ab(c'+c)
011
abc
000
001
010
011
100
101
110
111
cout
0
0
0
1
0
1
1
1 010
010
a(b+b')c
110
b
001
000
a
101
c
100
cout = bc + ab + ac
What about larger sub-cubes?
011
111
110
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111
b
001
000
a
101
c
100
ab’c’ + ab’c + abc’ + abc
ac’ + ac + ab = a + ab = a
• Both b & c change, a is
asserted & remains constant.
EECS150 - Lec7-Bool2
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Karnaugh Map Method
• K-map is an alternative method of representing the TT and
to help visual the adjacencies.
a
b
0 1
0
1
ab
c
00 01 11 10
0
1
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ab
cd
00 01 11 10
00
01
11
10
5 & 6 variable k-maps possible
EECS150 - Lec7-Bool2
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Karnaugh Map Method
• Examples
a
b
a
0 1
0 0 1
1 0 1
b
f=a
0 1
0 1 1
1 0 0
g = b'
ab
c
00 01 11 10
0 0 0 1 0
1 0 1 1 1
cout = ab + bc + ac
ab
c
00 01 11 10
0 0 0 1 1
1 0 0 1 1
f=a
1. Circle the largest groups possible.
2. Group dimensions must be a power of 2.
Spring 2002
EECS150 - Lec7-Bool2
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K-maps (cont.)
ab
c
00 01 11 10
0 1 0 0 1
1 0 0 1 1
f = b'c' + ac
Circling Zeros
ab
cd
00
01
11
10
00
1
0
1
1
01
0
1
1
1
11
0
0
1
1
10
1
0
1
1
f = c + a'bd + b'd'
(bigger groups are better)
ab
cd
00
01
11
10
00
1
0
1
1
01
0
1
1
1
11
0
0
1
1
10
1
0
1
1
f = (b' + c + d)(a' + c + d')(b + c + d')
Spring 2002
EECS150 - Lec7-Bool2
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BCD incrementer example
abcd
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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wxyz
0001
0010
0011
0100
0101
0110
0111
1000
1001
0000
- - - - - - - - - - - - - - - - - - -
w
x
ab
cd
00
01
11
10
ab
00
0
0
0
0
00
01
11
10
11
-
11
1
0
-
cd
00
01
11
10
y
ab
cd
01
0
0
1
0
00
0
1
0
1
01
0
1
0
1
11
-
00
0
0
1
0
cd
00
01
11
10
w=
x=
y=
z=
EECS150 - Lec7-Bool2
11
-
11
0
0
-
z
ab
11
0
0
-
01
1
1
0
1
00
1
0
0
1
01
1
0
0
1
11
-
11
1
0
-
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Higher Dimensional K-maps
de
00
a=1
bc
00 01 11
10
ab = 10
10
11
10
10
ab = 11
10
00 01 11
10
00 01 11
10
00 01 11
10
00
10
11
10
00
10
11
10
cd
00 01 11
10
11
10
00 01 11
a=0
ef
00
ab = 01
00
10
11
10
ab = 00
00
10
11
10
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EECS150 - Lec7-Bool2
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Multi-level Combinational Logic
a
d
f
 Example: reduced sum-of-products form
x = adf + aef + bdf + bef + cdf + cef + g
 implementation in 2-levels with gates:
cost: 7-input OR, 6 3-input AND
50 transistors + 25 wires
(19 literal plus 6 internal)
delay: 3-input AND gate delay + 7-input OR gate delay
 Factored form:
x = (a + b +c)(d + e)f + g
a
b
c
d
e
f
g
cost: 1 3-input OR, 2 2-input OR, 1 3-input AND
x
20 transistors
delay: 3-input OR + 3-input AND + 2-input OR
Which is faster?
In general: Using multiple levels (more than 2) will reduce the cost. Sometimes also
delay.
Sometime a tradeoff between cost and delay.
Spring 2002
EECS150 - Lec7-Bool2
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Multi-level Combinational Logic
Example: F = abc + abd +a’c’d’ + b’c’d’
let x = ab y = c+d
a
b
c
f = xy + x’y’
a
b
d
a
c
d
b
c
d
a
b
x
f
c
d
y
No convenient hand methods for multi-level logic simplification:
1 CAD Tools, example misII (UCB)
2 exploit some special structure, example adder
Are these optimizations still relevant for LUT implementations?
Spring 2002
EECS150 - Lec7-Bool2
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NAND-NAND & NOR-NOR Networks
DeMorgan’s Law:
(a + b)’ = a’ b’
b + b = (a’ b’)’
(a b)’ = a’ + b’
(a b) = (a’ + b’)’
=
=
=
=
push bubbles or introduce in pairs or remove pairs.
Spring 2002
EECS150 - Lec7-Bool2
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NAND-NAND & NOR-NOR Networks
• Mapping from AND/OR to NAND/NAND
a)
b)
c)
d)
a
b
c
d
Spring 2002
EECS150 - Lec7-Bool2
Page 17
NAND-NAND & NOR-NOR Networks
•
a)
a
b
c
d
a
b
c
d
•
•
Mapping AND/OR to NOR/NOR
a
b
c
d
a)
b)
b)
c)
c)
OR/AND to NAND/NAND
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Mapping OR/AND to NOR/NOR
pair
a'
b'
c'
d'
EECS150 - Lec7-Bool2
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Multi-level Networks
F = a(b + cd) + bc’
c
d
b
a
f
b
c'
Convert to NANDs (note fanout)
a
b
c
d
Spring 2002
EECS150 - Lec7-Bool2
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EXOR Function
Parity, addition mod 2
x xor y = x’y + xy’
x y xor xnor
00 0 1
x
01
10
1
1
0
0
y
11
0
1
x'
y
x
y'
Another approach:
x
y
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0
1
if x=0 then y else y'
EECS150 - Lec7-Bool2
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