IMS Workshop: Technologies for THZ Integrated Systems (WMD)
Monday, June 3, 2013, Seattle, Washington (8AM-5PM)
Transistors for THz Systems
Mark Rodwell, UCSB
rodwell@ece.ucsb.edu
Co-Authors and Collaborators:
Teledyne HBT Team:
M. Urteaga, R. Pierson, P. Rowell, B. Brar, Teledyne Scientific Company
Teledyne IC Design Team:
M. Seo, J. Hacker, Z. Griffith, A. Young, M. J. Choe, Teledyne Scientific Company
UCSB HBT Team:
J. Rode, H.W. Chiang, A. C. Gossard , B. J. Thibeault, W. Mitchell
Recent Graduates: V. Jain, E. Lobisser, A. Baraskar,
UCSB IC Design Team:
S. Danesgar, T. Reed, H-C Park, Eli Bloch
WMD: Technologies for THZ Integrated Systems
RFIC2013, Seattle, June 2-4, 2013
1
DC to Daylight. Far-Infrared Electronics
*ITU band designations
How high in frequency can we push electronics ?
1982: ~20 GHz
9
10
10
10
11
sub-mm-wave
THF*
0.3-3THz
1-0.1 mm
far-IR: 0.3-6 THz
12
10
Frequency (Hz)
mid-IR
6-100 THz
50-3 m
13
10
14
10
optical
385-790 THz
10
mm-wave
EHF*
30-300 GHz
10-1 mm
~2030: 3THz
near-IR
100-385 THz
3-0.78 m
microwave
SHF*
3-30 GHz
10-1 cm
2012: 820 GHz
** IR bands as per ISO 20473
15
10
...and what we would be do with it ?
100+ Gb/s wireless networks
Video-resolution radar
→ fly & drive through fog & rain
near-Terabit
optical fiber links
2
THz Transistors: Not Just For THz Circuits
500 GHz digital logic
→ fiber optics
precision analog design
at microwave frequencies
→ high-performance receivers
Higher-Resolution
Microwave ADCs, DACs,
DDSs
THz amplifiers→ THz radios
→ imaging, communications
3
THz Communications Needs High Power, Low Noise
Real systems with real-world weather & design margins, 500-1000m range:
Will require:
3-7 dB Noise figure, 50mW- 1W output/element, 64-256 element arrays
→ InP or GaN PAs and LNAs, Silicon beamformer ICs
4
THz Communications Needs High Power, Low Noise
Real systems→ LNAs with low Fmin, PAs with high Psat & high PAE
Comparing technologies
InP HEMTs give the best noise. InP HBT & GaN HEMT compete for the PA.
CMOS is great for signal processing, but noise, power, PAE are poor.
Harmonic generation is low power, inefficient. Harmonic mixing is noisy. 5
III-V PAs and LNAs in today's wireless systems...
http://www.chipworks.com/blog/recentteardowns/2012/10/02/apple-iphone-5-the-rf/
THz Device Scaling
7
nm Transistors, Far-Infrared Integrated Circuits
IR today→ lasers & bolometers → generate & detect
Far-infrared ICs: classic device physics, classic circuit design
It's all about the interfaces: ...wire resistance,... ...& charge density.
contact and gate dielectrics...
...heat,...
band structure and
density of states !
8
Transistor scaling laws: ( V,I,R,C,t ) vs. geometry
Fringing Capacitances
Depletion Layers
C 

A
T
C finging / L ~ 
T
2v
TIC 
Bulk and Contact Resistances
R   contact / A
contact te rms dominate
2) IC interconne ct capacitanc es
C finging / L ~ 
Thermal Resistance
I max 4vsat (Vappl   )

A
T2
1) FET fringing capacitanc es
L
PIC
K th L
Ttransistor ~
P
L
ln  
K th L  W 
Available quantum states to carry current
→ capacitance,
transconductance
contact resistance
9
THz & nm Transistors: State Density Limits
2-D: FET
capacitance
current
C DOS
3-D: BJT
q 2 m*

2 2
23 / 2 q 5 / 2 m * V 3 / 2

3 2  2
1/ 2
J sheet
2
conductivity    q    2 
c
   3
   
1/ 2
 n1/ 2
q 3 m *V 2
J
4 2 3
 q2   3 
 c      
    8 
2/3
 n2/ 3
# of available quantum states / energy
determines FET channel capacitance
FET and bipolar transistor current
access resistance of Ohmic contact
10
Bipolar Transistor Design
We
Tb
 b  T 2 Dn
2
b
Wbc
Tc
 c  Tc 2v sat
Ccb  Ac /Tc
I c ,max  vsat Ae (Vce,operating  Vce,punch-through) / T
emitter
length LE 
2
c
P
T 
LE

 Le 
1  ln  
 We 

Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
11
Bipolar Transistor Design: Scaling
We
Tb
 b  T 2 Dn
2
b
Wbc
Tc
 c  Tc 2v sat
Ccb  Ac /Tc
I c ,max  vsat Ae (Vce,operating  Vce,punch-through) / T
emitter
length LE 
2
c
P
T 
LE

 Le 
1  ln  
 We 

Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
12
Breakdown: Never Less than the Bandgap
band-band tunneling: base bandgap
impact ionization: collector bandgap
13
FET Design
C gd  C gs, f  Wg
gate width W 
g m  C g ch  (v / Lg )
C g ch 
g
LgWg
Tox /  ox  Twell / 2 well  (q 2 /well state density )
 voltage division ratio between 

v  
 the above three capacitors 
RDS  Lg /(Wg v )
RS  RD 
1 / 2
1

transport mass
contact
LS/DWg
14
FET Design: Scaling
C gd  C gs, f  Wg
gate width W 
g m  C g ch  (v / Lg )
C g ch 
g
LgWg
Tox /  ox  Twell / 2 well  (q 2 /well state density )
 voltage division ratio between 

v  
 the above three capacitors 
RDS  Lg /(Wg v )
RS  RD 
1 / 2
1

transport mass
contact
LS/DWg
15
FET Design: Scaling
C gd  C gs, f  Wg
2:1
2:1
constant
g m  C g ch  (v / Lg )
gate width W 
g
2:1
2:1
2:1
C g ch 
2:1
LgWg
2:1
Tox /  ox  Twell / 2 well  (q 2 /well state density )
2:1
2:1
2:1
 voltage division ratio between 

v  
three capacitors 
constant
 the above
constant
constant
RDS  Lg /(Wg v )
2:1
2:1
RS  RD 
constant
2:1
1 / 2
1

transport mass
constant
contact 4:1
LS/DWg
2:1
16
Changes required to double transistor bandwidth
LG
gate width WG 
FET parameter
gate length
current density (mA/m), gm (mS/m)
transport effective mass
channel 2DEG electron density
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
change
decrease 2:1
increase 2:1
constant
increase 2:1
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
We
emitter
length LE 
constant voltage, constant velocity scaling
HBT parameter
emitter & collector junction widths
current density (mA/m2)
current density (mA/m)
collector depletion thickness
base thickness
emitter & base contact resistivities
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
nearly constant junction temperature → linewidths vary as (1 / bandwidth) 2 17
THz & nm Transistors: what needs to be done
Metal-semiconductor interfaces (Ohmic contacts): very low resistivity
Dielectric-semiconductor interfaces (Gate dielectrics---FETs only): thin !
Ultra-low-resistivity (~0.25 W-m2 ), ultra shallow (1 nm), ultra-robust (0.2 A/m2 ) contacts
Mo
Ru
InGaAs
InGaAs
Heat
L
TIC 
Available quantum states to carry current
PIC
K th L
P
L
Ttransistor ~
ln  
K th L  W 
→ capacitance,
transconductance
contact resistance
18
THz InP HBTs
19
Scaling Laws, Scaling Roadmap
Tb
scaling laws: to double bandwidth
HBT parameter
emitter & collector junction widths
current density (mA/m2)
current density (mA/m)
collector depletion thickness
base thickness
emitter & base contact resistivities
We
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
emitter
Wbc
Tc
length LE 
150 nm device
20
HBT Fabrication Process Must Change... Greatly
32 nm width base & emitter contacts...self-aligned
32 nm width emitter semiconductor junctions
Contacts:
1 W-m2 resistivities
70 mA/m2 current density
~1 nm penetration depths
→ refractory contacts
nm III-V FET, Si FET processes have similar requirements
21
Needed: Greatly Improved Ohmic Contacts
Pt/Ti/Pd/Au
~5 nm
Pt contact
penetration
(into 25 nm base)
22
Ultra Low-Resistivity Refractory Contacts
-6
Barasakar et al
IEEE IPRM 2012
P-InGaAs
2
Contact Resistivity (Wcm )
10
N-InGaAs
N-InAs
Mo
Mo
-7
10
Ir
W
Mo
-8
32 nm node
requirements
10
-9
10
18
19
20
21
10
10
10
10
-3
concentration (cm )
17
18
19
20
10
10
10
10
-3
concentration (cm )
18
19
20
21
10
10
10
10
-3
concentration (cm )
In-situ: avoids surface contaminants
Refractory: robust under high-current operation
Low penetration depth, ~ 1 nm
Contact performance sufficient for 32 nm /2.8 THz node.
23
Ultra Low-Resistivity Refractory Contacts
-6
Barasakar et al
IEEE IPRM 2012
P-InGaAs
2
Contact Resistivity (Wcm )
10
N-InGaAs
N-InAs
Mo
Mo
-7
10
Ir
W
Mo
-8
32 nm node
requirements
10
-9
10
18
19
20
21
10
10
10
10
-3
concentration (cm )
17
18
19
20
10
10
10
10
-3
concentration (cm )
18
19
20
21
10
10
10
10
-3
concentration (cm )
Schottky Barrier is about one lattice constant
what is setting contact resistivity ?
what resistivity should we expect ?
24
Ultra Low-Resistivity Refractory Contacts
-6
Barasakar et al
IEEE IPRM 2012
P-InGaAs
2
Contact Resistivity (Wcm )
10
N-InGaAs
N-InAs
Mo
Mo
-7
10
Ir
W
Mo
-8
32 nm node
requirements
10
-9
10
18
19
20
21
10
10
10
10
-3
concentration (cm )
17
18
19
20
10
10
10
10
-3
concentration (cm )
18
19
20
21
10
10
10
10
-3
concentration (cm )
2/3
Zero - barrier contact resistivit y :
    8 
1 1






 2/3


c
2
 q2  3
(state density and
T
n
   
quantum - reflectivi ty limit)
n  carrier concentrat ion
T  transmissi on coefficien t
 c  0.1 W  m 2 at n  7 1019 / cm 3 .
25
Refractory
EmitterImproved
ContactsOhmic Contacts
Needed: Greatly
negligible
penetration
26
HBT Fabrication Process Must Change... Greatly
tall, narrow contacts: liftoff fails !
control undercut
→ thinner emitter
thinner emitter
→ thinner base metal
thinner base metal
→ excess base metal resistance
Undercutting of emitter ends
{101}A planes: fast
{111}A planes: slow
27
Sub-200-nm Emitter Contact & Post
Refractory contact, refractory post→ high-J operation
Sputter+dry etch→ 50-200nm contacts
Liftoff aided by TiW/W interface undercut
Dielectric sidewalls
TiW
SiNx
100 nm
W
Mo
HBT: V. Jain. Process: Jain & Lobisser
28
RF Data: 25 nm thick base, 75 nm Thick Collector
25
U
Gains (dB)
20
H
15
10
5
21
f = 530 GHz

f
max
0
10
10
Required dimensions obtained
but poor base contacts on this run
= 750 GHz
11
10
Frequency (Hz)
12
10
E. Lobisser, ISCS 2012, August, Santa Barbara
29
DC, RF Data: 100 nm Thick Collector
f
32
f = 480 GHz
U
H
P = 20 mW/m
2
P = 30 mW/m
30
2
A = 0.22 x 2.7 m
2

25
21
je
20
15
I
b,step
= 200 A
10
20
5
0
16
A = 0.22 x 2.7 m
2
BV
0
1
2
V
je
12
0 9
10
e
10
10
-3
10
-5
b
P = 33.5 mW/m2
Vcb = 0.7 V
-1
11
10
10
Frequency (Hz)
ce
Solid line: V
Dashed: V
cb
cb
4
5
= 0.7V
20
= 0V
15
n = 1.19
c
10
n = 1.87
10
-7
10
-9
12
10
3
(V)
b
I
b

5
I
c
0
0.2 0.4 0.6 0.8
Vbe (V)
0
1
30

4
J = 20.4 mA/m2
10
c
8
Ic = 12.1 mA
I , I (A)
Gain (dB)
e
24
= 1.0 THz
J (mA/m )
28
max
Jain et al
IEEE DRC 2011
2
THz InP HBTs From Teledyne
Chart 31
Urteaga et al, DRC 2011, June
31
Towards & Beyond the 32 nm /2.8 THz Node
Base contact process:
Present contacts too resistive (4Wm2)
Present contacts sink too deep (5 nm) for target 15 nm base
→ refractory base contacts
Emitter Degeneracy:
Target current density is almost 0.1 Amp/m2 (!)
Injected electron density becomes degenerate.
transconductance is reduced.
→ Increased electron mass in emitter
32
Base Ohmic Contact Penetration
~5 nm
Pt contact
penetration
(into 25 nm base)
33
Refractory Base Process (1)
Blanket liftoff; refractory base metal
low contact resistivity
low penetration depth
Patterned liftoff; Thick Ti/Au
low bulk access resistivity
base surface not exposed to photoresist chemistry: no contamination
low contact resistivity, shallow contacts
low penetration depth allows thin base, pulsed-doped base contacts34
Refractory Base Process (2)
-5
10
P-InGaAs
Contact Resistivity, Wcm
2
-6
10
-7
10
32 nm node
requirement
-8
10
B=0.8 eV
-9
10
0.6 eV
0.4 eV
0.2 eV
step-barrier
Landauer
-10
10
18
2.5 1020
doping, 1/cm3
19
20
21
10
10
10
10
-3
Hole Concentration, cm
Increased surface doping:
reduced contact resistivity,
but increased Auger recombination.
20
2 10
2 nm doping pulse
1.5 1020
1 1020
→ Surface doping spike at most 2-5 thick.
19
5 10
0 100
0
5
10
15
depth, nm
20
25
Refractory contacts do not penetrate;
compatible with pulse doping.
35
Refractory Base Ohmic Contacts
Ru / Ti / Au
<2 nm
Ru contact
penetration
(surface removal
during cleaning)
36
Degenerate Injection→ Reduced Transconductance
10
2
10
1
Boltzmann
(-V )>>kT/q
2
J(mA/m )
be
10
10
-1
10
-2
10
-3
Current varies exponentially with Vbe
J  J s exp( qVbe / kT ).
Transconductance is high
g m / AE  J
0
-0.3
J  J s exp( qVbe / kT ).
-0.2
-0.1
0
V -
0.1
0.2
be
37
Degenerate Injection→ Reduced Transconductance
10
2
10
1
Fermi-Dirac
Boltzmann
(-V )>>kT/q
2
J(mA/m )
be
10
10
-1
10
-2
10
-3
Current varies exponentially with Vbe
J  J s exp( qVbe / kT ).
Transconductance is reduced
0
-0.3
-0.2
-0.1
0
V -
0.1
0.2
be
38
Degenerate Injection→ Reduced Transconductance
10
2
10
1
Fermi-Dirac
Boltzmann
(-V )>>kT/q
2
J(mA/m )
be
Highly degenerate limit:
10
0
Highly degenerate
(V ->>kT/q
be
10
-1
10
-2
10
-3
current varies as the square of bias
J  m (Vbe   )
*
E
2
-0.3
q 3m *
J  2 3 (Vbe   ) 2
8 
-0.2
-0.1
0
V -
0.1
0.2
be
39
Degenerate Injection→ Reduced Transconductance
10
2
10
1
Fermi-Dirac
Boltzmann
(-V )<<kT/q
2
J(mA/m )
be
Highly degenerate limit:
10
0
Highly degenerate
(V ->>kT/q
be
10
-1
10
-2
10
-3
current varies as the square of bias
J  m (Vbe   )
*
E
2
Transconductance varies as J1/2
g m / AE  mE* J
...and as (m*)1/2
-0.3
q 3m *
J  2 3 (Vbe   ) 2
8 
-0.2
-0.1
0
V -
0.1
0.2
be
At & beyond 32 nm, we must increase the emitter effective mass.
40
Degenerate Injection→Solutions
At & beyond 32 nm, we must increase the emitter (transverse) effective mass.
Other emitter semiconductors:
no obvious good choices (band offsets, etc.).
Emitter-base superlattice:
increases transverse mass in junction
evidence that InAlAs/InGaAs grades are beneficial
Extreme solution (10 years from now):
partition the emitter into small sub-junctions, ~ 5 nm x 5 nm.
parasitic resistivity is reduced progressively as sub-junction areas are reduced.
41
3-4 THz Bipolar Transistors are Feasible.
4 THz HBTs realized by:
Extremely low resistivity contacts
Extreme current densities
Processes scaled to 16 nm junctions
Impact:
efficient power amplifiers
and complex signal processing
from 100-1000 GHz.
42
InP HBT: Key Features
512 nm node:
high-yield "pilot-line" process, ~4000 HBTs/IC
256 nm node:
Power Amplifiers: >0.5 W/mm @ 220 GHz
highly competitive mm-wave / THz power technology
128 nm node:
>500 GHz f , >1.1 THz fmax , ~3.5 V breakdown
breakdown* f = 1.75 THz*Volts
highly competitive mm-wave / THz power technology
64 nm (2 THz) & 32 nm (2.8 THz) nodes:
Development needs major effort, but no serious scaling barriers
1.5 THz monolithic ICs are feasible.
43
Can we make a 1 THz SiGe Bipolar Transistor ?
InP
emitter 64
2
SiGe
18
0.6
nm width
Wm2 access 
18
0.7
nm contact width,
Wm2 contact 
Key challenge: Breakdown
15 nm collector → very low breakdown
collector 53
36
2.75
15
125
1.3?
nm thick
mA/m2
V, breakdown
Also required:
low resistivity Ohmic contacts to Si
very high current densities: heat
f
fmax
1000
2000
GHz
GHz
Simple physics clearly drives scaling
transit times, Ccb/Ic
→ thinner layers, higher current density
high power density → narrow junctions
base
small junctions→ low resistance contacts
64
2.5
1000
2000
PAs
1000 1000
GHz
digital 480
480
GHz
(2:1 static divider metric)
Assumes collector junction 3:1 wider than emitter.
Assumes SiGe contacts no wider than junctions 44
THz InP Bipolar Transistor Technology
Goal:
extend the operation of electronics
to the highest feasible frequencies
THz InP Heterojunction Bipolar Transistors
1 THz device
60-600 GHz IC examples; demonstrated & in fab
Scaling roadmap through 3 THz
220 GHz
power amplifiers
ultra-efficient 85 GHz
power amplifiers
188 mW,
33% PAE
182 mW
50 GHz sample/hold 40 GHz op-amp
100 GHz ICs for
*electronic*
demultiplexing
of WDM optical
communications
40 Gb/s phase-locked
coherent optical receivers
Enabling Technologies :
~30 nm fabrication processes, extremely low resistivity (epitaxial, refractory) contacts,
extreme current densities, doping at solubility limits, few-nm-thick junctions
Teledyne Scientific: moving THz IC Technology towards aerospace applications
1.1 THz pilot IC process
204 GHz digital logic (M/S latch)
670 GHz amplifier
614 GHz
fundamental
oscillator
(VCO)
300 GHz fundamental phase-lock-loop
Vtune
VBB
VEE
Vout
THz InP HEMTs
and
III-V MOSFETs
46
Changes required to double transistor bandwidth
LG
gate width WG 
FET parameter
gate length
current density (mA/m), gm (mS/m)
transport effective mass
channel 2DEG electron density
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
change
decrease 2:1
increase 2:1
constant
increase 2:1
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
We
emitter
length LE 
constant voltage, constant velocity scaling
HBT parameter
emitter & collector junction widths
current density (mA/m2)
current density (mA/m)
collector depletion thickness
base thickness
emitter & base contact resistivities
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
nearly constant junction temperature → linewidths vary as (1 / bandwidth) 2 47
FET scaling challenges...and solutions
Gate barrier under S/D contacts → high S/D access resistance
addressed by S/D regrowth
High gate leakage from thin barrier, high channel charge density
(almost) eliminated by ALD high-K gate dielectric
Other scaling considerations:
low InAs electron mass→ low state density capacitance → gm fails to scale
increased m* , hence reduced velocity in thin channels
minimum feasible thickness of gate dielectric (tunneling) and channel
48
III-V MOS
Peak transconductance; VLSI-style FET:
2.5 mS/micron
~85% of best THz InAs HEMTs
VDS=0.05 V
2.4
2.0
VDS=0.5 V
2.0
1.6
1.2
1.6
Lg = 40 nm
(SEM)
1.2
0.8
0.8
0.4
0.4
0.0
-0.2
0.0
0.2
0.4
Gate Bias (V)
Sanghoon Lee
0.6
0.0
Peak Transconductance (mS/m)
2.4
Gm (mS/m)
Current Density (mA/m)
III-V MOS will soon surpass HEMTs
in RF performance
2.8
90 [011]
0 [01-1]
2.4
2.0
1.6
1.2
0.8
0.4
0.0
at Vds=0.5V
0.1
1
Gate length (m)
40 nm devices are nearly ballistic
49
FET Drain Current in the Ballistic Limit
 mA   Vgs  Vth 

  
J  K1   84
 m   1 V 
normalized drive current K
1
0.35
3/ 2
, where K1 
InGaAs <--> InP
1  (c

g  m* mo
1/ 2
*
dos,o / cequiv )  g  ( m / mo )
Si

3/ 2
g=2
g=1
0.3
cequiv  ( 1/cox  1/cdepth )1
0.25
 εSiO2 /EET
0.2
0.3 nm
0.4 nm
0.15
0.1
0.05

g  # band minima
cdos,o  q 2 m0 / 2 2
0.6 nm
EET=Equivalent Electrostatic Thickness
=ToxSiO2/ox+TinversionSiO2/semiconductor
0
0.01
0.1
m*/m
EET=1.0 nm
1
o
In ballistic limit, current and transconductance are set by:
channel & dielectric thickness, transport mass, state density
50
Transit delay versus mass, # valleys, and EOT
1/ 2
Lg
 m* 

  1 Volt 
Qch
 
 ch 
 K 2  
where K 2   
7


ID
 2.52 10 cm/s   Vgs  Vth 
 m0 
EOT=1.0 nm
2
1.5
Normalized transit delay K
1/ 2
1/ 2
* 
 cdos,o
m
 1 
g 

ceq
mo 

0.6 nm
1 nm
0.4 nm
0.6 nm
0.4 nm
Si, GaN
1
cequiv  ( 1/cox  1/csemi )1
InGaAs
0.5
 εSiO2 /EOT
g=1, isotropic bands
g=2, isotropic bands
EOT includes wavefunction depth term
(mean wavefunction depth*SiO2 /semiconductor )
0
0
0.05
0.1
0.15
0.2
0.25
m*/m
0.3
0.35
0.4
o
Low m* gives lowest transit time, lowest Cgs at any EOT.
51
3000
f
2000
4000
2500
max
1500
3500
3000
fmax
2000
f

f , GHz
2500
canonical scaling
stepped # of bands
 transport only
, GHz
FET Scaling: fixed vs. increasing state density
1500
1000
500
500
0
2.5
0
1000
SCFL static divider clock rate, GHz
drain current density, mA/m
1000
mA/m→ VLSI metric
2
1.5
1
0.5
200 mV gate overdrive
0
0
10
20
30
40
gate length, nm
50
Need higher state density for ~10 nm node
60
SCFL divider speed
800
600
400
200
0
0
10
20
30
40
gate length, nm
50
60
52
2-3 THz Field-Effect Transistors are Feasible.
3 THz FETs realized by:
Ultra low resistivity source/drain
High operating current densities
Very thin barriers & dielectrics
or
MOSFET
high-barrier HEMT
Gates scaled to 9 nm junctions
Impact:
Sensitive, low-noise receivers
from 100-1000 GHz.
3 dB less noise →
need 3 dB less transmit power.
53
4-nm / 5-THz FETs: Challenges
4 nm
Gate dielectric
0.1 nm EOT: UTB
0.2 nm EOT: fin
Estimated (WKB) tunneling
current is just acceptable at
0.2 nm EOT.
Channel thickness
0.8 nm: UTB
1.6 nm: fin
atomically flat
How can we make
a 1.6 nm thick fin,
or a 0.8 nm thick body ?
54
Thin wells have high scattering rate
Scattering probabilit y  1 / m T
Sakaki
2 6
q well
.
APL 51, 1934 (1987).
Need single-atomic-layer control of thickness
Need high quantization mass mq.
55
III-V vs. CMOS: A false comparison ?
UTB Si MOS UTB III-V MOS
III-V THz
MOS/HEMT
III-V THz HEMT
III-V MOS has a reasonable chance of future use in VLSI
The real THz / VLSI distinction:
Device geometry optimized for high-frequency gain
vs. optimized for small footprint and high DC on/off ratio.
56
Conclusion
57
THz and Far-Infrared Electronics
IR today→ lasers & bolometers → generate & detect
Far-infrared ICs: classic device physics, classic circuit design
It's all about classic scaling: ...wire resistance,...
contact and gate dielectrics...
...heat,...
...& charge density.
Even 1-3 THz ICs
will be feasible
band structure and
density of quantum states
(new!).
58
(backup slides follow)
59
Electron Plasma Resonance: Not a Dominant Limit
T 1
Lkinetic 
A q 2nm*
T
1
Rbulk 
A q 2nm* m
dielectric relaxation frequency scattering frequency
1 Rbulk
1 / 2
f scatter 
f dielecic 
2 Lkinetic
Cdisplacement Rbulk
1
1 


2m
2 
n - InGaAs
3.5  10 / cm
19
p - InGaAs
7  10 / cm
19
3
Cdisplacement 
A
T
plasma frequency
1 / 2
f plasma 
LkineticCdisplacement
800 THz
7 THz
74 THz
80 THz
12 THz
31 THz
3
60