Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Short Course, IEEE Bipolar / BiCMOS Circuits and Technology Meeting, 9 October 2011, Atlanta, Georgia
100-1000 GHz Bipolar ICs:
Device and Circuit Design Principles
Mark Rodwell, UCSB
Munkyo Seo, Teledyne Scientific
Collaborators:
Teledyne HBT Team:
M. Urteaga, R. Pierson, P. Rowell, B. Brar, Teledyne Scientific Company
Teledyne IC Design Team:
J. Hacker, Z. Griffith, A. Young, M. J. Choe, Teledyne Scientific Company
UCSB HBT Team:
V. Jain, E. Lobisser, A. Baraskar, J. Rode, H.W. Chiang, A. C. Gossard , B. J. Thibeault, W. Mitchell
UCSB IC Design Team:
S. Danesgar, T. Reed, Eli Bloch, H-C Park, J-H Kim
rodwell@ece.ucsb.edu , mseo@teledyne-si.com
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Motivation /
Overview
DC to Daylight. Far-Infrared Electronics
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
How high in frequency can we push electronics ?
10
9
10
mm-wave
30-300 GHz
10
10
11
far-IR
(sub-mm)
0.3-3THz
mid-IR
3-30 THz
12
10
Frequency (Hz)
10
13
near-IR
30-450 THz
10
14
optical
450-900 THz
microwave
3-30 GHz
10
...and what would be do with it ?
0.3- 3 THz imaging systems
0.3-3 THz radio: vast capacity
bandwidth, # channels
0.1-1 Tb/s
optical fiber links
15
THz Transistors: Not Only For THz Circuits
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
500 GHz digital logic
→ fiber optics
THz amplifiers→ THz radios
→ imaging, sensing,
communications
precision analog design
at microwave frequencies
→ high-performance receivers
Higher-Resolution
Microwave ADCs, DACs,
DDSs
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
ICs to 600 GHz : Teledyne and UCSB
570 GHz
fundamental
VCO
M. Seo, TSC
CSIC 2010
Vtune
VBB
VEE
Vout
430 GHz
low-noise
amplifier
M. Seo, TSC
other ICs by J. Hacker
204 GHz static
frequency divider
(ECL master-slave
latch)
Z. Griffith, TSC
CSIC 2010
340 GHz
dynamic
frequency
divider
M. Seo, TSC
IEEE MWCL 2010
300 GHz
fundamental
PLL
M. Seo, TSC
IMS 2011
40 GHz
op-amp with
54 dBm IP3
at 2 GHz
Z. Griffith, TSC
IMS 2011
220 GHz
48 mW
power
amplifier
T. Reed, UCSB
CSIC 2011
Other ICs in
design:
30-40 GS/s track/hold
optical PLLs
coherent optical receivers
340 GHz arrays
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
At High Frequencies The Atmosphere Is Opaque
Mark Rosker
IEEE IMS 2007
THz Bipolar Transistors: Where Next ?
array transmitters: critical for sub-mm-wave radio / radar
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
340 GHz
670 GHz
1080 GHz
Preceived N receive N transmit 2 R

e
2
Ptransmit
16
R
32 x 32 array → 60-90 dB increased SNR →vastly increased range
100
increasing
f , f max , ( I bias / Cload )
80
60
40
20
0
6
10
10
7
8
9
10
10
10
10
Frequency, Hz
11
10
12
10
32 nm / 3 THz node, beyond
Stage Voltage Gain, dB
Stage Voltage Gain, dB
HBT / HEMT integration for mixed-signal
100
decreasing
g m , x  ( Rin || Rload || Rout )
80
gain @ 100 MHz
design frequency
60
40
20
0
6
10
10
7
8
9
10
10
10
10
Frequency, Hz
11
10
12
10
III-V NFET vs. Si PFET
active loads:
much lower Cload/Ibias
LSI @ 128 nm node:
scaled interconnects
high packing density
→ speed, power
Transition to production
R&D→ pilot → foundry
design tools, reliability, scaled interconnects
CMOS control integration: 3-D, flip chip
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Bipolar Transistors:
Models,
Scaling Laws,
State of Art,
Roadmaps
Bipolar Transistor: Structure & Models
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Rbe   / gm
gm  qI E / nkT
Cbe  C je  g m ( b   c )
 b  Tb2 / 2 Dn  Tb / vthermal
 c  Tc / 2v"sat"
 nkT

1
nkT

  base   collector  C je
 Cbc 
 Rex  Rcoll 
2f
qI E
 qI E

Base-Collector Distributed RC Parasitics
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Rex   contact,emitter / Aemitter
emitter
length LE 
Rspread   sWe / 12 LE
Rgap   sWgap / 4 LE
Rspread,contact   sWbc / 6 LE
Rcontact   contact,base / Abase_ contacts
Ccb ,e  Aemitter / Tc
Ccb , gap  Agap / Tc
Ccb ,contact  Abase_ contacts / Tc
RbbCcb Time Constant, Fmax , Simple Hybrid- model
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
f max 
f 8RbbCcbi where
 cb  RbbCcbi  Ccb ,contactRcontact
Vaidyanathan & Pulfrey
IEEE Trans. Elect. Dev.
Feb. 1999
 Ccb , gap ( Rcontact  Rspread,contact  Rgap / 2)
 Ccb ,e ( Rcontact  Rspread,contact  Rgap  Rspread )
Rbb  true total base resistance
Ccbi  Ccbx  true total Ccb
Ccbi : Ccbx ratio set to fit f max from above
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Key 2nd-Order Effects in III-V HBTs: Omitted for Brevity
Current - induced velocity overshoot : decreases  c
Nakajima, Japanese Journal of Applied Physics, Feb. 1997
Voltage modulation of collector velocity : increases  c
Partial Ccb cancellati on by collector velocity modulation .
Betser and Ritter , IEEE Trans. Elect. Dev., April 1999
Urteaga & Rodwell, IEEE Trans. Elect. Dev., July 2003
Degenerate electron injection into base : increases Rex
Rodwell, Le, Brar, Proc IEEE , February 2008
Jain & Rodwell, IEEE Electron. Dev. Lett., to be published (2011)
2.5
8
10
2
10
1
10
0
-0.2 V
7
e
cb
1
6
0.0 V
5
0.2 V
0.5
1
1.5
2
2.5
3
3.5
2
inverse current density, 1/J,m /mA
10
-2
10
-3
Equivalent series
resistance approximation
V = 0.6 V
cb
0
0
Fermi-Dirac
-1
4
2
0
10
Boltzmann
3
0.5
J(mA/um^2)
C /A (fF/m2)
1.5
ec
tau , ps
2
2.5
5
7.5
2
J (mA/m )
10
12.5
-0.3
-0.2
-0.1
V -
0
be
e
More detailed information regarding III-V bipolar transistor physics and design:
http://www.ece.ucsb.edu/Faculty/rodwell/publications_and_presentations/publications/2009_may_IPRM_short_course_rodwell.pdf
0.1
0.2
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Space Charge, Kirk Effect, Minimum Ccb charging time
SiGe HBT
InP DHBT
Collector Depletion Layer Collapse
Vcb,min    (qN d )(Tc2 / 2 )
Collector Field Collapse
Vcb    ( J / vsat  qN d )(Tc2 / 2 )
 J max  2veff (Vcb  Vcb,min  2 ) / Tc2
Note that Vbe   , hence (Vcb   )  Vce
Ccb VLOGIC / I C  Acollector Tc VLOGIC
VLOGIC  Acollector  TC


IC  
VCE  VCE,min   Aemitter  2veff
Collector capacitance charging time minimized by setting J = Jmax
...if so, charging time scales linearly with collector thickness.




Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Space-Charge-Limited Current (Kirk effect) in BJTs
Decreased ( f , f max ) , increased Ccb at high J .
Increase in Vce , sat with increased J
Kirk thres hold increases with increased Vce .
dVce
Tc2
 Rspacecharge 
dI c
2vsat Aeffective
500
0.6 V
cb
400
0.2 V
cb
0.0 V
where the effective collector
current flux area is
Aeffective  LE WE  2TC 
f (GHz)
cb
-0.2 V
300

cb
f , -0.3 V

200
100
0
2
cb
4
6
8
2
J (mA/um )
10
12
e
8
A = 0.6 x 4.3 m
jbe
16
-0.2 V
I
b step
= 180 uA
35
12
2
Je (mA/m )
30
10
6
0.0 V
5
0.2 V
4
3
V = 0.6 V
40
25
Peak f , f
8
t
max
20
6
15
4
10
2
5
0
0
cb
2
0
2.5
5
7.5
J (mA/m2)
e
10
12.5
0
0.5
1
1.5
V
ce
(V)
2
2.5
c
e
cb
I (mA)
cb
V =0V
14
7
C /A (fF/m2)
2
Bipolar Transistor Design
We
Tb
 b  T 2 Dn
2
b
Wbc
Tc
 c  Tc 2v sat
Ccb  Ac /Tc
I c ,max  vsat Ae (Vce,operating  Vce,punch-through) / T
2
c
P
T 
LE

 Le 
1  ln  
 We 

Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
emitter
length LE 
Bipolar Transistor Design: Scaling
We
Tb
 b  T 2 Dn
2
b
Wbc
Tc
 c  Tc 2v sat
Ccb  Ac /Tc
I c ,max  vsat Ae (Vce,operating  Vce,punch-through) / T
2
c
P
T 
LE

 Le 
1  ln  
 We 

Rex  contact /Ae
 We Wbc  contact
 
Rbb  sheet 

 12 Le 6 Le  Acontacts
emitter
length LE 
Breakdown is Never Less Than The Bandgap
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Bipolar Transistors: Scaling Laws, Scaling Roadmap
scaling laws: to double bandwidth
HBT parameter
emitter & collector junction widths
current density (mA/m2)
current density (mA/m)
collector depletion thickness
base thickness
emitter & base contact resistivities
InP HBT scaling roadmap
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
We
Wbc
Tb
emitter
Tc
length LE 
150 nm device
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Recent InP HBT Results: Urteaga et al, DRC 2011
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Recent InP HBT Results: Jain et al, DRC 2011
30nm emitter, 30nm base, 100nm collector
f
32
H
Gain (dB)
24
= 1.0 THz
f = 480 GHz
U
28
max

21
20
16
A = 0.22 x 2.7 m2
je
12
Ic = 12.1 mA
8
J = 20.4 mA/m2
e
P = 33.5 mW/m2
Vcb = 0.7 V
4
0 9
10
10
11
12
10
10
Frequency (Hz)
10
2
P = 20 mW/m
2
P = 30 mW/m
25
je
15
I
b,step
= 200 A
e
10
5
0
BV
0
1
2
V
ce
3
(V)
10
-3
10
-5
Solid line: V
Dashed: V
4
5
cb
cb
= 0.7V
20
= 0V
15
n = 1.19
c
10
n = 1.87
b
c
20
-1
b
2
A = 0.22 x 2.7 m
I , I (A)
2
10
10
-7
10
-9
I
b

5
I
c
0
0.2 0.4 0.6 0.8
Vbe (V)
0
1

J (mA/m )
30
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Can we make a 1 THz SiGe Bipolar Transistor ?
InP
emitter 64
2
SiGe
18
0.6
nm width
m2 access 
18
0.7
nm contact width,
m2 contact 
Key challenge: Breakdown
15 nm collector → very low breakdown
collector 53
36
2.75
15
125
1.3?
nm thick
mA/m2
V, breakdown
Also required:
low resistivity Ohmic contacts to Si
very high current densities: heat
f
fmax
1000
2000
GHz
GHz
Simple physics clearly drives scaling
transit times, Ccb/Ic
→ thinner layers, higher current density
high power density → narrow junctions
base
small junctions→ low resistance contacts
64
2.5
1000
2000
PAs
1000 1000
GHz
digital 480
480
GHz
(2:1 static divider metric)
Assumes collector junction 3:1 wider than emitter.
Assumes SiGe contacts no wider than junctions
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Interconnects
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
III-V MIMIC Interconnects -- Classic Substrate Microstrip
W
Zero ground
inductance
in package
Thick Substrate
→ low skin loss
 skin 
1
 r1 / 2 H
High via
inductance
12 pH for 100 m substrate -- 7.5  @ 100 GHz
lines must be
widely spaced
Line spacings must be
~3*(substrate thickness)
H
Brass carrier and
assembly ground
IC with backside
ground plane & vias
interconnect
substrate
No ground plane
breaks in IC
near-zero
ground-ground
inductance
TM substrate
mode coupling
IC vias
eliminate
on-wafer
ground
loops
kz
Strong coupling when substrate approaches ~d / 4 thickness
ground vias must be
widely spaced
all factors require very thin substrates for >100 GHz ICs
→ lapping to ~50 m substrate thickness typical for 100+ GHz
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Coplanar Waveguide
No ground vias
No need (???) to
thin substrate
Hard to ground IC
to package
+V
+V
+V
0V
Parasitic microstrip mode
ground plane breaks → loss of ground integrity
-V
0V
substrate mode coupling
or substrate losses
kz
III-V:
semi-insulating
substrate→ substrate
mode coupling
Silicon
conducting substrate
→ substrate
conductivity losses
+V
0V
Parasitic slot mode
Repairing ground plane with ground straps is effective only in simple ICs
In more complex CPW ICs, ground plane rapidly vanishes
→ common-lead inductance → strong circuit-circuit coupling
poor ground integrity
loss of impedance control
ground bounce
coupling, EMI, oscillation
40 Gb/s differential TWA modulator driver
note CPW lines, fragmented ground plane
35 GHz master-slave latch in CPW
note fragmented ground plane
175 GHz tuned amplifier in CPW
note fragmented ground plane
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
III-V MIMIC Interconnects -- Thin-Film Microstrip
narrow line spacing → IC density
no substrate radiation, no substrate losses
fewer breaks in ground plane than CPW
... but ground breaks at device placements
InP 34 GHz PA
(Jon Hacker , Teledyne)
still have problem with package grounding
...need to flip-chip bond
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
W
Zo ~
o  H 


 r1/ 2  W  H 
H
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip
narrow line spacing → IC density
Some substrate radiation / substrate losses
No breaks in ground plane
... no ground breaks at device placements
still have problem with package grounding
InP 150 GHz master-slave latch
...need to flip-chip bond
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
InP 8 GHz clock rate delta-sigma ADC
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
If It Has Breaks, It Is Not A Ground Plane !
signal line
line 1
“ground”
signal line
“ground”
line 2
ground plane
common-lead inductance
coupling / EMI due to poor ground system integrity is common in high-frequency systems
whether on PC boards
...or on ICs.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
No clean ground return ? → interconnects can't be modeled !
35 GHz static divider
interconnects have no clear local ground return
interconnect inductance is non-local
interconnect inductance has no compact model
8 GHz clock-rate delta-sigma ADC
thin-film microstrip wiring
every interconnect can be modeled as microstrip
some interconnects are terminated in their Zo
some interconnects are not terminated
...but ALL are precisely modeled
InP 8 GHz clock rate delta-sigma ADC
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
VLSI mm-wave interconnects with ground integrity
narrow line spacing → IC density
no substrate radiation, no substrate losses
negligible breaks in ground plane
negligible ground breaks @ device placements
still have problem with package grounding
...need to flip-chip bond
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
Also:
Ground plane at *intermediate level* permits
critical signal paths to cross supply lines, or other
interconnects without coupling.
(critical signal line is placed above ground,
other lines and supplies are placed below ground)
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Modeling Interconnects, Passives in Tuned ( RF ) IC's
Interconnects are tuning elements
Narrow bandwidths→ precision is critical
Initial IC simulation uses CAD-systems' library of passive element models.
Final design: 2.5-Dimensional electromagnetic simulation of:
lines, junctions, stubs, capacitors, resistors, pads.
150-200 GHz HBT amplifier, Urteaga et al, IEEE JSSCC , Sept. 2003
185GHz HBT amplifier, Urteaga et al,
IEEE IMS, May. 2001
1-180GHz HBT amplifier, Agarwal et al,
IEEE Trans MTT , Dec.. 1998
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Modeling Interconnects: Digital & Mixed-Signal IC's
longer interconnects:
lines terminated in Zo → no reflections.
Shorter interconnects:
lines NOT terminated in Zo .
But they are *still* transmission-lines.
Ignore their effect at your peril !
L  Z 0 ,
C   / Z0 ,
If length << wavelength,
or line delay<<risetime,
short interconnects behave
as lumped L and C.
 l /v
Design Flow: Digital & Mixed-Signal IC's
All interconnects: thin-film microstrip environment.
Continuous ground on one plane.
2.5-D simulations run on representative lines.
various widths, various planes
same reference (ground) plane.
Simulation data manually fit to CAD line model
effective substrate r , effective line-ground spacing.
Width, length, substrate of each line
entered on CAD schematic.
rapid data entry, rapid simulation.
Resistors and capacitors:
2.5-D simulation→ RLC fit
RLC model used in simulation.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Network analyzer
Calibration...
on-wafer LRL
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
On-Wafer Through-Reflect-Line (TRL) Calibration
reference plane
Through
225um 225um
Through line should be long for large probe separation.
Minimizes probe-probe coupling.
Measurements normalized to the line characteristic impedance.
open
short
225um
225um
Reflect
ΔL
Line
ΔL= 90 deg @center frequency.
/8<ΔL<3/8
225um
Device
Under Test
DUT
225um
Either open or short needed.
Standards need not be accurate.
"Open" must have G closer to
that of open than that of short.
Ports 1 & 2 must be symmetric.
Please see also:
http://www.ece.ucsb.edu/Faculty/rodwell/publications_and_presentations/publications/204vg.ppt
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
On-Wafer TRL: Ongoing Issues
High-fmax transistors have very small ( Ccb → Y12 → S12 )
Measurements show small background Y12.
...even with extended reference planes.
Particular difficulty in extracting Mason's Unilateral gain.
→ Corrupts fmax measurement, model extraction.
Measurements normalized to line Z0.
...line impedance is complex at lower frequencies.
→ must correct for complex Zo in measurements.
excessive line resistance degrades precision.
ZO 
R ( j )  jL
j C
TRL precision greatly impaired if lines couple to substrate;
CPW line standards do not work well.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Verification of 140-220GHz TRL Calibration
Through
Line
S(2,2)
S(1,1)
S(2,2)
S(1,1)
S(2,2)
S(1,1)
Open
M. Seo
freq (140.0GHz to 200.0GHz)
freq (140.0GHz to 200.0GHz)
freq (140.0GHz to 200.0GHz)
-0.2
dB(S(1,2))
dB(S(2,1))
-0.4
0.4
-25
-0.8
0.2
-30
0.0
-0.2
-1.0
-35
-40
-0.4
-45
-0.6
-50
140
150
160
170
freq, GHz
180
190
200
140
-80
140
150
160
170
freq, GHz
180
190
200
phase(S(2,1))
dB(S(1,2))
dB(S(2,1))
dB(S(1,2))
dB(S(2,1))
-0.6
150
160
170
180
190
200
freq, GHz
m10
m10
freq=150.0GHz
phase(S(2,1))=-91.553
-100
-120
-140
140
150
160
170
freq, GHz
180
190
200
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Difficulties with 140-220GHz TRL Calibration
Data on two layouts of 65 nm MOSFET
Measured Y-parameters correlate
reasonably with expected device model.
10
MSGMAG_dB_pfg
MSGMAG_dB_ibm
MAG/MSG, dB
9
Small errors in measured 2-port
parameters result in large changes in
Unilateral gain and Rollet's stability
factor; neither measurement is credible.
8
7
6
( K<1 )
5
4
3
2
Y12 appears to be the key problem.
1
0
1E12
9E11
8E11
7E11
6E11
5E11
4E11
3E11
2E11
1E11
IC Sij measurements are fine.
Transistor fmax measurements are hard.
20
gain", dB
"Unilateral
Um_ibm_dB
15
10
Um_pfg_dB
Um_pfg
Um_ibm
gain", linear
"Unilateral
freq, Hz
20
5
0
-5
U < 0 (!)
-10
-15
10*log10|U| (?)
18
16
14
12
10
8
U
6
4
Y21  Y12
2
4G11G22  G21G12 
2
0
-20
1E12
9E11
8E11
freq, Hz
7E11
200
6E11
190
5E11
freq, GHz
180
4E11
170
3E11
160
2E11
150
1E11
140
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
50+ GHz
Mixed-Signal
& ECL design:
Principles &
Examples
High Speed ECL Design
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Followers associated with inputs, not outputs
Emitters never drive long wires.
(instability with capacitive load)
Double termination for least ringing, send or receive termination for
moderate-length lines, high-Z loading saves power but kills speed.
Current mirror biasing is more compact.
Mirror capacitance→ ringing, instability.
Resistors provide follower damping.
High Speed ECL Design
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Layout: short signal paths at gate centers, bias sources surround core.
Inverted thin film microstrip wiring.
Key: transistors in on-state
operate at Kirk limited-current.
→ minimizes Ccb/Ic delay.
Key: transistors designed for minimum
ECL gate delay*, not peak (f, fmax).
*hand expression, charge-control analysis
205 GHz divider, Griffith et al, IEEE CSIC, Oct. 2010
Example: 8:1 205 GHz static divider
in 256 nm InP HBT.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
mm-wave Op-Amps for Linear Microwave Amplification
Griffith et al, IEEE IMS, June. 2011
output power, dBm
linear response
50
Feedback Factor, dB
Reduce distortion with
strong negative feedback
40
20
10
0
8
10
increasing feedback
2-tone
intermodulation
increasing
loop bandwidth
30
9
10
10
10
Frequency, Hz
11
10
Even for 2 GHz operation,
loop bandwidths must 20-40 GHz.
R. Eden
need very fast transistors
input power, dBm
physically small feedback loop;
bias components surround active core.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
mm-wave Op-Amps for Linear Microwave Amplification
Griffith et al, IEEE IMS, June. 2011
current-mode analog design
...node impedances kept low
with transimpedance loading
→ high bandwidth
Virtual-ground input stage, Miller feedback
around output stage, makes feedback
insensitive to generator & load impedances.
...critical for stability in a 50 GHz loop !
(what will the op-amp be connected to ?)
Zt-stage and loop nesting for high gain
even with fast resistor-loaded circuits
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
mm-wave Op-Amps for Linear Microwave Amplification
Griffith et al, IEEE IMS, June. 2011
Griffith et al, IEEE IPRM, May. 2008
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
40 GSample/s Sample/Hold *Design*
Saeid Daneshgar
master-slave track-hold
target 40 GS/s, 6 b (??)
256 nm InP HBT
ECL
ECL
TAS
TIS
layout: ECL buffer.
ECL
layout: TASTIS.
Bias and transmission-line design strongly follows controlled-impedance ECL examples.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
RF-IC design
Principles &
Examples
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
RF-IC Design: Simple & Well-Known Procedures
1: (over)stabilize at the design frequency
guided by stability circles
2: Tune input for Fmin (LNAs) or output for Psat (PAs)
3: Tune remaining port for maximum gain
4: Add out-of-band stabilization.
There are many ways to tune port impedances: microstrip lines, MIM capacitors, transformers
Choice guided by tuning losses. No particular preferences.
30
U
25
Common-base gain is however reduced by:
base (layout) inductance
emitter-collector layout capacitance.
MSG/MAG, dB
For BJT's, MAG/MSG usually highest for common-base.
20
→ preferred topology.
Common emitter
15
Common base
10
Common Collector
5
0
10
100
Frequency, GHz
1000
Power Amplifier Design (Cripps method)
Current, mA
For maximum saturated output power,
& maximum efficiency
Pmax  1 8Vmax  Vmin I max
device intrinsic output must see
optimum loadline set by:
breakdown, maximum current, maximum power density.
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
100
80
breakdown
60
200 mW
40
20
100 mW
0
0
1
2
3
4
5
6
7
V or V (V)
ce
ds
parasitic C's and R's represented
by external elements...
ammeter monitors intrinsic
junction current
without including
capacitive currents
...(Vcollector-Vemitter )
measures voltage
internal to series parasitic
resistances...
8
10
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
3-stage 150-GHz Amplifier; IBM 65 nm CMOS
Acknowledgement:
IBM
5
M. Seo, B. Jagannathan, J. Pekarik, M. Rodwell, IEEE JSSCC, Dec. 2009
0
10
-5
S21(meas)
S21(sim)
S21 (measured using power sensor)
S11 (meas)
S11 (sim)
S22 (meas)
S22 (sim)
S21
S-parameter (dB)
5
-10
-15
-20
140
150
160
170
0
-5
S11 (meas)
-10
180
K-factor
190S22
200
3
2
1
0
Frequency (GHz)
-15
153 GHz-20
153 GHz
140
158.4 GHz
158.4 GHz
153 GHz
158.4 GHz
S11 (sim)
150
160
170
180
S21(meas)
S21(sim)
S21 (measured
S11 (meas)
S11 (sim)
S22 (meas)
S22 (sim)
Stability
factor (K)
140
160
180
140
160 (GHz)
180
Frequency
Frequency (GHz)
190
200
Frequency (GHz)
Frequency
(GHz)
Dummy-prefilled microstrip lines
Gain
5
20
Pout
0
153 GHz
153
GHz
153.0GHz
158.4
GHz
158.4GHz
158.4 GHz
153 GHz
158.4 GHz
-5
15
10
-10
5
PAE
10
Power
Power Added
Added Efficiency
Efficiency (%)
(%)
25
25
0
-20
-15
5
-10
-5
Input
Inputpower
power (dBm)
(dBm)
0
5
20
ncy (%)
-15
m)
Output
power
(dBm)
Output
Gain (dB)
power
(dBm),
10
220 GHz, 48 mW HBT Power Amplifier
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
T. Reed et al, IEEE CSIC, Oct. 2011, to be presented.
4-cell design: Psat >48 mW @ 220 GHz
schematic of single cell
8-cell design: not yet fully tested: Psat = ?
Technology:
Teledyne 250 nm InP HBT
Right-side-up thin-film microstrip wiring.
Breaks in ground plane minimized.
High Frequency Bipolar IC Design
Rodwell and Seo, IEEE BCTM Short Course, Oct. 2011, copyright
Digital, mixed-signal, RF-IC (tuned) IC designs----at very high frequencies
Even at 670 GHz, design procedures differ little from that at lower
frequencies: classic IC design extends readily to the far-infrared.
Key considerations: Tuned ("RF") ICs
Rigorous E&M modeling of all interconnects & passive elements
Continuous ground plane → required for predicable interconnect models.
Higher frequencies→ close conductor planes→ higher loss, lower current
Key considerations: digital & mixed-signal :
Transmission-line modeling of all interconnects
Continuous ground plane → required for predicable interconnect models.
Unterminated lines within blocks; terminated lines interconnecting blocks.
Analog & digital blocks design to naturally interface to 50 or 75.
Next: TMIC designs for 340 GHz, 670 GHz transceivers.