Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
IEEE CSIC Short Course, RF and High Speed CMOS, Nov. 12, 2006, San Antonio, Texas
mm-Wave IC Design:
The Transition from III-V to CMOS Circuit
Techniques
Patrick Yue, Mark Rodwell, UCSB
Outline
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Background
– Emerging mm-wave applications
– Open design issues for mm-Wave CMOS
• CMOS for mm-wave design
– Optimizing CMOS device performance – layout & bias
– On-chip inductors in CMOS
– Cell-based device modeling and design methodology
– State of the art CMOS mm-Wave design examples
• mm-Wave design techniques
– Device characterization issues
– Unconditionally stable, gain-matched amplifier design procedure
– Tuned amplifier, power amplifier design examples
– On-chip transmission line design
• Summary
• References
Emerging mm-Wave Wireless Applications
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
(~10 dB/km at sea level)
•
Unlicensed 60-GHz band for Gbit wireless link:
– Outdoor, point-to-point wireless link
– Wireless High-Definition Multimedia Interface (HDMI)
• Licensed point-to-point wireless link in E-band
(71-76, 81-86 GHz, and 92-95 GHz)
• Vehicular radar at 76-77 GHz
• 94-GHz band for high-resolution imaging
Questions:
Can we leverage scaled
CMOS to produce more
cost-effective products
and enable new markets?
Recent Evolution for CMOS RF
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
RF
Front-end
Lower power,
cost and size
Baseband DSP
(D. Su, et al. ISSCC 2002.)


0.25-mm CMOS
5-GHz RF transceiver
(S. Mehta, et al. ISSCC 2005.)
• 0.18-mm CMOS
• RF + baseband DSP
But difficult to migrate below 0.18mm even for RF SoC...
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
State of the Art mm-Wave IC: 330 GHz 16-Finger Power Amp
designs in progress: Michael Jones
device: 5 V, 650 GHz fmax InP DHBT
wiring: thin film microstrip with 2 um BCB
Challenges:
line losses are very high
lines > 60 W are not feasible → increases Q of output tuning
lines of required impedance are narrow → limits on DC current
small unmodeled parasitics will de-tune design
....must maintain microstrip environment to device vias
with negligible lengths of unmodeled random interconnects
Open Design Issues
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• RF CMOS design are by and large lumped circuits
• mm-Wave design are traditionally distributed circuits
• How will mm-Wave CMOS be designed?
– Assuming that we will integrate an entire transceiver,
should each block be impedance-matched?
– Do we need new design flow / methodology?
– Should all interconnect be modeled as T-line and be
impedance-controlled?
– Do we need a well-controlled global ground (plane)?
• How to optimize CMOS device performance?
CMOS Device Parameter Scaling Trend
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Challenges for RF/mm-Wave in 0.13-mm CMOS and Beyond
• High mask cost ($0.5M – $1M)
– only makes sense if integration level increases,
e.g. RF + large DSP, or mm-wave transceiver
• Lack of a streamline RF/mm-wave design flow
• Negative impact of technology scaling
– Device
• Process variations
Strongly depend
• Model uncertainty
on layout
• Interconnect parasitic variations
– Circuit
• Low voltage headroom due to reduced Vdd
 Develop
a parasitic-aware design methodology
 Explore low-voltage circuit techniques
High Frequency Figures of Merit
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Minimize Rg, Rs, and Rsub for better performance
• Layout and biasing are both critical
• Minimize Rg, Rs, and Rsub for better performance
• Layout and biasing are both critical
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Complete Macro Model
• Core model (baseline BSIM model)
• Interconnect RC (3D EM field solver)
• Gate and substrate resistances (physical model)
Drain
Core
Rd
Model
Rsub1
Cgd_ext
Gate
Rg
Cds_ext
Cgd_ext
Rds
Rsub2
Rs
Source
Bulk
Gate Resistance Components
Ref. 16
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Gate Electrode Resistance
Ref. 16 & 18
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Channel Conductance
Gch  Gst  Ged

Ref. 16
L
W
(ac effect – channel charge distribution modulated by gate voltage,
derived based on diffusion current)
Layout Guideline for Gate Resistance
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Multi-finger layout in RF MOSFET is common to minimize Rgate
(at the expense of more parasitic capacitance)
• Typical finger width for 0.25um device is about 5 um whereas in 0.13um CMOS
is 1.5 um
• Total gate width ranges from a few 10’s of micron for LNA, mixer & VCO
to a few millimeters for PA
• Reltd (poly resistance) scales with 1/n2
• External portion of Rgeltd (contact resistance) scale with 1/n
• Rch is independent of n to the first order
Substrate Resistance Model
Active Region
STI
Region
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
(R. Chang, et al. TED 2004.)
• Active and STI regions have different sheet resistances
• Resistances in x and y directions modeled as parallel resistors
Analytical Model of Substrate Resistance
Ref. 17
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Optimization of Substrate Resistance
Ref. 17
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Interconnect RC Modeling Using 3D Field Solver
Source
Gate
Drain
Bottom view showing
substrate taps
Top view
Width (mm)
nf
Cgs_wire (fF)
Cgd_wire (fF)
Cds_wire (fF)
2.0
4
2.42
1.61
1.41
• Wire capacitance per finger is extracted
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
RF Macro Model vs. Measurement (16 x 2mm/0.12 m m)
Core Model
Macro Model
15
575
Macro Model
19
Measurement
Measurement
10
5
550
Gm [mS]
Rout [Ohm]
Rin [Ohm]
Core Model
525
18
17
Core Model
500
16
Macro Model
Measurement
0
5
6
7
8
9
Frequency [GHz]
475
0
10
2
Macro Model
Macro Model
40
2
4
6
8
Frequency [GHz]
10
Cout [fF]
45
40
15
Measurement
Cfb [fF]
Measurement
Cin [fF]
15
0
10
Core Model
Core Model
50
4
6
8
Frequency [GHz]
35
30
35
10
5
Core Model
Macro Model
Measurement
30
0
2
4
6
8
Frequency [GHz]
10
25
0
2
4
6
8
Frequency [GHz]
10
0
0
2
4
6
8
Frequency [GHz]
Rg = 9.8 W, Rsub = 475 W, Cgs_ext= 4 fF, Cgd_ext= 2.9 fF, Cds_ext= 5.2 fF
10
Optimized Layout for fT, fmax and NF
• Parallel Rg improves fmax and NFmin
• Gate connected at both ends
• Source drain metals do not overlap
• Bulk contacts surround device
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Optimal Finger Width for fT
(E. Morifuji, et al. VLSI 1999.)
fT (GHz)
(L.Tiemeijer, et al. IEDM 2004.)
Finger width (mm)
• fT approaches vsat / L deep in
velocity saturation
Finger width 
No. of fingers 
Capacitance 
fT 
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Optimal Finger Width for fmax
(L.Tiemeijer, et al. IEDM 2004.)
fmax (GHz)
fmax (GHz)
(E. Morifuji, et al. VLSI 1999.)
Finger width (mm)
Finger width (mm)
• Reducing Rg vs. increasing Cgg
• For 0.13-mm, optimal finger width is ~2 mm
• Optimal finger width decreases with device scaling
Optimal Finger Width for NF
Finger width (um)

Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Finger width (um)
Noise due to Rg and Rsub can be minimized through layout
optimization
Ref. 11
Optimal Biasing for fT, fMAX and NFMIN
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Peak fT, fMAX and NFMIN characteristic current densities largely
unchanged across technology nodes and foundries
• NFMIN (0.15mA/µm) and peak fMAX (0.2mA/µm) are close 
LNAs simultaneously optimized for noise and high gain
• In CMOS PAs optimum current swing when biased at
0.3mA/µm
10%
degradation
in fMAX
Optimum
Current Swing
Bias
Source: Yao, RFIC 2006. - U. of Toronto
Frequency Response of On-Chip Inductor Q
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
First Patterned Ground Shield (PGS)
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Inserted between the
inductor and substrate
• PGS fingers connected in
a “star” shape
• Terminates the E field
• No effect on the H field
• Improves isolation
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Self-Shielded Stacked Inductors for high SRF
25 mm
• Self-shielded layout can effectively boost-strap
the overlap capacitance *
• 1-nH inductor can be achieved in 25x25 mm2
using M5 through M8 in a 0.13-mm CMOS 8-metal
process
* C.-C. Tang, JSSC, April 2002.
Top view
Bottom view
4 layer (M5-M8)
3 layer (M6-M8)
2 layer (M7-M8)
Systematic mm-wave Design with P-Cells
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Stand-alone single device model is insufficient
• Interconnect model accuracy limited by digital RC extraction
• Test structure layout
 actual circuit layout
Design Flexibility
Design Automation
Model Scalability
Model Accuracy
Scalable
Sub-Circuit P-Cells


Leverage the insight to device layout optimization
Exploit the modularity at the sub-circuit level
Sample P-Cell Layouts and Circuit Models
Diff Pair
D1
D2
Cross-Coupled
Pair
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Cascode
D
D1&G2
G2
SS
SS
G1
G1
G2
D2&G1
S
B
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Sub-Circuit Cell Library for mm-wave Design
Inductor and transformer PCell
D
D
G2
G2
B
G1
G1
S
S
Two transistor sub-circuit PCell
Tuned IF Amplifier
7 mm
7 mm
2.71 mm
7 mm
5 mm
Routing interconnect PCell


A unified design and modeling framework
Each sub-circuit P-Cell has its scalable circuit model
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
mm-wave P-Cell Characterization Test Structures
• Measured S-parameters to validate macro models
• UMC 0.13-mm CMOS with 8 copper layers
Outline
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• Background
– Emerging mm-wave applications
– Open design issues for mm-Wave CMOS
• CMOS for mm-wave design
– Optimizing CMOS device performance – layout & bias
– On-chip inductors in CMOS
– Cell-based device modeling and design methodology
– State of the art CMOS mm-Wave design examples
• mm-Wave design techniques
– Device characterization issues
– Unconditionally stable, gain-matched amplifier design procedure
– Tuned amplifier, power amplifier design examples
– On-chip transmission line design
• Summary
• References
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
140-220 & 220-330 GHz On-Wafer Network Analysis
• HP8510C VNA,
Oleson Microwave Lab mm-wave
Extenders
• coplanar wafer probes made by:
GGB Industries, Cascade Microtech
•connection via short length of
waveguide
GGB Wafer Probes
330 GHz available with bias Tees
• Internal bias Tee’s in probes for biasing
active devices
•measurements to 100 GHz
can be in coax.
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
High Frequency Device Gain Measurements : Standard Pads
Measuring wideband transistors is very hard ! Much harder than measuring amplifiers.
Determining fmax in particular is extremely difficult on high-fmax or small devices
Standard "short pads"
must strip pad capacitance
must strip pad inductance--or ft will be too high !
cal can be bad due to substrate coupling
make pads small, and shield them from substrate
cal can be bad due to probe coupling
use small probe pitch, use well-shielded probes
35
35
21
25
Gains (dB)
25
Gains (dB)
U
30
h
30
20
2
15
A
10
I = 20.6 mA, V = 1.53 V
jbe
= 0.6 x 4.3 um
c
ce
2
J = 8.0 mA/um , V = 0.6 V
e
5
t
max
9
10
A
10
I = 20.6 mA, V = 1.53 V
10
10
Frequency (Hz)
jbe
= 0.6 x 4.3 um
c
ce
2
J = 8.0 mA/um , V = 0.6 V
e
cb
f = 450 GHz, f
= 490 GHz
t
max
= 490 GHz
k
0
0
10
2
15
5
cb
f = 450 GHz, f
MAG/MSG
20
11
12
10
9
10
10
10
10
Frequency (Hz)
11
12
10
High Frequency Measurements : On-Wafer LRL
Extended Reference planes
transistors placed at center of long on-wafer line
LRL standards placed on wafer
large probe separation → probe coupling reduced
still should use the best-shielded probes available
Problem: substrate mode coupling
method will FAIL if lines couple to substrate modes
→ method works very poorly with CPW lines
need on wafer thin-film microstrip lines
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
CPW
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Unilateral Power Gain
1) Cancel device feedback w ith external lossless feedback
 Y12  S12  0
2) Match input and output
Resulting power gain is Mason' s Unilatera l Gain
Y21  Y12
U
4G11G22  G21G12 
2
Monolithic amplifiers are not easily made unilateral
 U mostly of historical relevance to IC design
30
U
25
 U useful for extrapolat ion to find f max
In III - V FETs, U shows peak from Cds - Rs - Rd interactio n
 U hard to use for f max extrapolat ion
MSG/MAG, dB
For simple BJT model, U rolls off at - 20 dB/decade
20
Common emitter
15
Common base
10
Common Collector
5
For bulk CMOS, Cds is sheilded by substrate
 U should be OK for f max extrapolat ion
0
10
100
Frequency, GHz
1000
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design Tools: Power Gain Definitions
Transducer Gain
Zs
Available Gain
Insertion Gain
Zs=Zo
Zs
Sij
ZL=Zo
Sij
ZL=Zout*
ZL
Vgen
Sij
Vgen
GT  Pload / Pav, gen
Vgen
GA  Pav,a / Pav, gen
load power
power available from generator
 general - case gain

Operating Gain
S21  Pav,a / Pav, gen
2
power available from amplifier
power available from generator
 gain with output matched

Maximum Available Gain

power delivered to Z o load
power available from Z o generator
 gain in a 50 Ohm enviroment
After impedance-matching:
Sij,matched
Zs=Zin*
Sij
Vgen
Zs=Zin*
load power

power delivered from generator
 gain with input matched
match
Sij,raw
match
ZL=Zo
ZL=Zout*
ZL
GP  Pload / Pgen,delivered
Zs=Zo
Sij
Vgen
GMax  Pav,a / Pgen ,delivered
power available from amplifier
power delivered from generator
 gain with both ports matched

Vgen
2
S21,matched  Gmax, raw
S11,matched  S22,matched  0
...MAG may not exist...
....but only if unconditionally stable...
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design Tools: Stability Factors, Stability Circles
in  S11  L
S11
S12 S21
1  S22L
S21
S22
S12
out  S22  S
S12 S21
1  S11S
S21
L
Load Stability Circle
S
S11
S22
S12
Source Stability Circle
Unconditio nally stable
(stable with all L , S  if :
K  Rollet stability factor
1  S11  S22  det 2 S 

1
2 S21S12
2
2
and B  stability measure
 1  S11  S22  det 2 S   0
2
Values of L which make
Values of S which make
in  1  beyond lies negative Rin
out  1  beyond lies negative Rout
Negative port impedance→ negative-R oscillator
Tuning for highest gain→ infinite gain (oscillation)
2
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design Tools: Maximum Stable Gain
Maximum stable gain  MSG

circles at 50 GHz
S21 Y21
Z

 21
S12 Y12
Z12
17 W circle
stabilization
methods
17 W
Sij
Sij
Sij
Sij
~50 W
~75 W
~5-10 W
MSG
results
MAG
Adding series/shunt resistance
excludes source or load
from unstable regions → stabilizes
50 GHz
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design Procedure: Simple Gain-Matched Amplifier
First:
stabilize at the design frequency
source stability circle:
~5 Ohm on input will
overstabilize the device
S_StabCircle1
---device is potentially unstable
at 100 GHz design frequency
indep(S_StabCircle1) (0.000 to 51.000)
After stabilizing
(slightly over-stabilizing)
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design Procedure: Simple Gain-Matched Amplifier
Second:
Determine required interface impedances
available gain
operating gain
The Ga & Gp circles define the
source & load impedances
which the transistor must see
...it is necessary to OVERSTABILIZE
the device to move the Ga & Gp circles
towards the Smith chart center
Third:
Design Input & Output Tuning Networks
...to provide these impedances...
S,opt
L,opt
...added to device, the amplifier is not yet
complete...
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design Procedure: Simple Gain-Matched Amplifier
Forth:
Add out-of-band stabilization
potentially unstable
below 75 GHz
with frequency-selective
series stabilization
...caused only slight mistuning
& slight gain drop @ 100 GHz
...and is unconditionally
stable above 10 GHz
source & load stability circles & 10,20,...,100 GHz
Design Procedure: Effect of Line Losses
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Finally:
adjusting for line losses
high line skin effect losses → reduced gain
but line losses also increase stability factor
loss in gain are partly recovered
by reducing stabilization resistance &
re-tuning the design
line losses
--no analytical procedure; just component tweaking
line losses have severe impact
...in VLSI wiring environment
...particularly at 50 + GHz
...particularly with high-power amplifiers
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Tuned Amplifier Examples
20
3-stage cascode in 180 nm CMOS
15
10
5
0
-5
-10
-15
-20
30
35
40
45
50
8
III-V HBT small-signal amplifiers
6
S21, dB
4
2
0
-2
-4
140
150
160
170
180
190
200
210
220
Frequency, GHz
gain, dB
10
0
-10
-20
-30
140
150
160
170
180
190
200
210
220
Frequency (GHz)
Note: simple gain-tuned amplifiers → limited applications
Transmitters need power amplifiers: need output loadline-match, not gain-match
Receivers need low-noise amplifiers: need input noise-match, not gain-match
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Power Amplifier Design (Cripps method)
Current, mA
For maximum saturated output power, P  1 8V  V I
max
max
min
max
& maximum efficiency
device intrinsic output must see
optimum loadline set by:
breakdown, maximum current, maximum power density.
100
80
breakdown
60
200 mW
40
20
100 mW
0
0
1
2
3
4
5
6
7
V or V (V)
ce
ds
parasitic C's and R's represented
by external elements...
ammeter monitors intrinsic
junction current
without including
capacitive currents
...(Vcollector-Vemitter )
measures voltage
internal to series parasitic
resistances...
8
Power Amplifier Design (Cripps Method)
Design steps are
1) input stabilization (in-band)
2) output tuning for correct load-line
3) input tuning (match)
4) out-of-band stabilization
Example: 60 GHz, 30 mW PA, 130 nm BiCMOS
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design: Multi-Finger Power Amplifiers: Even-mode method
Even-mode equivalent circuit
-- Most multi-finger amplifiers do not use Wilkinson combiners: lines are too long
Even-mode equivalent circuit maps combined design into single-device design
Final design tuning (E&M simulation) with full circuit model
This method explicitly models all feed parasitics in a large multi-finger transistor
MUCH more reliable than using single lumped model for multi-finger device
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Design: Multi-Finger Amplifiers: spatial mode instabilities
If each transistor finger is individually stabilized, high-order modes are stable.
Amplifier layout usually does not allow sufficient space for this.
All spatial modes must then be stabilized.
etc...
Stabilization method: bridging resistors → parallel loading to higher-order modes
Select so that (ZS , ZL) presented to device lie in the stable regions
Design: Multi-Finger Amplifiers: Layout Examples
W-band InP HBT power amplifier - UCSB
mm-wave InP HBT power amplifier - Rockwell
mm-wave InP HBT power amplifier - Rockwell
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Low-Noise Amplifier Design-- device model
Basic model : Van der Ziel
G
SVV ,Rg  4kTRg (V / Hz )
2
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
SVV,Rg
Rg
Cgd
gmVg’s’ Gds
Sii,channel
SVV,Ri
SVV ,Ri  4kTRi (V / Hz )
2
D
Ri
SVV ,Rs  4kTRs (V / Hz )
2
Cgs
Cdb
Vg’s’
S II ,channel  4kTg m ( A2 / Hz )
Rs
2/3 : long channel, constant mobility

  2/3 under high field
Cross spectral - densities can be neglected
SVV,Rs
Csb
S
(B. Hughes, IEEE Trans MTT)
Simplified noise model
G
Rin
SVV,Rin
Cgd
gmxVg’s’ G
dsx Sii,channel
SVV ,Rin  4kTRin (V 2 / Hz )
S II ,channel  4kTΓ ' g m
D
Cgsx
Vg’s’
Cdb
'   as g m Rs  0
'  1 as g m Rs  
Csb
S
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Low-Noise Amplifier Design-- sketch of steps in Fmin calculation
Total input noise voltage & current spectal densities :
4kT
2
S En ( f )  4kTRin 
1  2fCgs  Rin2 (V 2 / Hz )
gm

SIn ( f ) 

4kT
2fCgs 2 ( A2 / Hz )
gm
S En I n ( f ) 
4kT
*

1  j 2fCgs Rin  j 2fCgs  (V  A / Hz )
gm
Noise figure with a particular source impedance :
2
F  1

S En  Z s S I n  2  Re Z s*SEn I n
4kT Re Z s 
Minimum noise figure
1 
Fmin  1 
2 S En S I n  Im S En I n
4kT 
 
Z opt  Ropt  jX opt 


 Im S En I n

S I n  S I n
S En

2
Zs
Vgen


 2 Re S En I n 




2
j

Im S En I n

Zs=Zo
SIn
noise
match
 Fukui Expressio n (rough)
Fmin
f

~ 1  2 ( Rs  Rg  Ri ) g m   signal 
 f 
Z opt ~
Rs  Rg  Ri  f 
1




g mx
 f signal  j 2f signalCgs
Zopt
Vgen
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Low-Noise Amplifier Design
Design steps are
1) output stabilization (in-band)
2) input tuning for Fmin
3) output tuning (match)
4) out-of-band stabilization
Zs=Zo
Zs
noise
match
Vgen
Discrepancy in input noise-match & gain-match
can be reduced by adding source inductance (R. Van Tuyl)
Example: 60 GHz, LNA, 130 nm BiCMOS
gain & noise circles after input matching
note compromise between gain & noise tune
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
III-V MIMIC Interconnects -- Classic Substrate Microstrip
W
Zero ground
inductance
in package
Thick Substrate
→ low skin loss
 skin 
1
 r1 / 2 H
High via
inductance
12 pH for 100 mm substrate -- 7.5 W @ 100 GHz
lines must be
widely spaced
Line spacings must be ~3*(substrate thickness)
H
Brass carrier and
assembly ground
IC with backside
ground plane & vias
interconnect
substrate
No ground plane
breaks in IC
near-zero
ground-ground
inductance
TM substrate
mode coupling
IC vias
eliminate
on-wafer
ground
loops
kz
Strong coupling when substrate approaches ~l d / 4 thickness
ground vias must be
widely spaced
all factors require very thin substrates for >100 GHz ICs
→ lapping to ~50 mm substrate thickness typical for 100+ GHz
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Coplanar Waveguide
No ground vias
No need (???) to
thin substrate
Hard to ground IC
to package
+V
+V
+V
0V
Parasitic microstrip mode
ground plane breaks → loss of ground integrity
-V
0V
substrate mode coupling
or substrate losses
kz
III-V:
semi-insulating
substrate→ substrate
mode coupling
Silicon
conducting substrate
→ substrate
conductivity losses
+V
0V
Parasitic slot mode
Repairing ground plane with ground straps is effective only in simple ICs
In more complex CPW ICs, ground plane rapidly vanishes
→ common-lead inductance → strong circuit-circuit coupling
poor ground integrity
loss of impedance control
ground bounce
coupling, EMI, oscillation
40 Gb/s differential TWA modulator driver
note CPW lines, fragmented ground plane
35 GHz master-slave latch in CPW
note fragmented ground plane
175 GHz tuned amplifier in CPW
note fragmented ground plane
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
III-V MIMIC Interconnects -- Thin-Film Microstrip
narrow line spacing → IC density
no substrate radiation, no substrate losses
fewer breaks in ground plane than CPW
... but ground breaks at device placements
InP mm-wave PA
(Rockwell)
still have problem with package grounding
...need to flip-chip bond
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
W
Zo ~
o  H 


 r1/ 2  W  H 
H
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip
narrow line spacing → IC density
Some substrate radiation / substrate losses
No breaks in ground plane
... no ground breaks at device placements
still have problem with package grounding
InP 150 GHz master-slave latch
...need to flip-chip bond
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
InP 8 GHz clock rate delta-sigma ADC
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
If It Has Breaks, It Is Not A Ground Plane !
signal line
line 1
“ground”
signal line
“ground”
line 2
ground plane
common-lead inductance
coupling / EMI due to poor ground system integrity is common in high-frequency systems
whether on PC boards
...or on ICs.
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
No clean ground return ? → interconnects can't be modeled !
35 GHz static divider
interconnects have no clear local ground return
interconnect inductance is non-local
interconnect inductance has no compact model
8 GHz clock-rate delta-sigma ADC
thin-film microstrip wiring
every interconnect can be modeled as microstrip
some interconnects are terminated in their Zo
some interconnects are not terminated
...but ALL are precisely modeled
InP 8 GHz clock rate delta-sigma ADC
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
VLSI mm-Wave Interconnects with Ground Integrity
narrow line spacing → IC density
no substrate radiation, no substrate losses
negligible breaks in ground plane
negligible ground breaks @ device placements
still have problem with package grounding
...need to flip-chip bond
thin dielectrics → narrow lines
→ high line losses
→ low current capability
→ no high-Zo lines
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Example: 150 GHz Master-Slave Latch
Device Technology:
500 nm InP HBT
Interconnects :
inverted thin-film microstrip
Design:
All lines modeled as microstrip lines
representative lines simulated in Agilent / Momentum
fit to simple lossy line model (loss, Zo, velocity)
Minimum input power (dBm)
20
10
0
-10
-20
-30
-40
0
20
40
60 80 100 120 140 160
frequency (GHz)
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
Example: 20 GHz DDFS Design (Rockwell)
designs in progress: MJ Choe
design target:
20 GHz clock rate
circuit topology:
ECL
device technology:
350 GHz (500 nm) InP HBT (Rockwell)
Interconnect technology:
inverted thin-film microstrip throughout
→ all lines are controlled-impedance
shorter lines:
unterminated, but modeled
longer lines:
modeled and
terminated
Summary
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
• At 90-nm or below, CMOS can be a cost-effective choice for
highly integrated mm-wave circuits
• Consideration for optimizing device layout and biasing are
very similar for mm-wave and RF
• Pre-characterized cell-based mm-wave design flow will be a
key enabler
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
References on other mm-Wave CMOS Efforts
• Prof. B. Brodersen and Prof. A. Niknejad – “Design considerations for 60 GHz
CMOS radios,”
IEEE Communications Magazine, Dec. 2004.
• Prof. A. Hajimiri – “A fully integrated 24-GHz phased-array transmitter in
CMOS,” IEEE JSSC, Dec. 2005.
• Prof. B. Razavi – “A 60-GHz CMOS receiver front-end” IEEE JSSC, Jan. 2006.
• Prof. F. Chang – “A 60GHz CMOS VCO using on-chip resonator with embedded
artificial dielectric for size, loss, and noise reduction,” 2006 ISSCC.
• Prof. J. Laskar – “60-GHz direct-conversion gigabit modulator/demodulator on
liquid-crystal polymer,” IEEE TMTT, Mar. 2006.
Yue & Rodwell, IEEE CSIC Short Course, Nov. 2006
In case
of questions