3rd Berkeley Symposium on Energy Efficient Electronic Systems, October 28-29, 2013
Prospects for High-Aspect-Ratio FinFETs
in Low-Power Logic
Mark Rodwell, Doron Elias
University of California, Santa Barbara
High Aspect Ratio Fins for Low-Power Logic
Fin thickness defined by Atomic layer epitaxy
→ nm thickness control
Fin height defined by sidewall growth
→ 200 nm high fins
InGaAs finFET:
8 nm thick fin
200 nm high
Enables ~4 nm fin bodies→ 8 nm gate length
10:1 more current per unit die area
→ smaller IC die area
complements lithographic scaling
Enables high speed, ultra low-power logic,
Vdd~300 mV
D. Elias, DRC 2013, June, Notre Dame
InGaAs NFET
height>> pitch
InGaAs PFET
Background: III-V MOS
3.2
VDS = 0.1 to 0.7 V
1.2
2.8
0.2 V increment
2.4
2.0
0.8
1.6
1.2
0.4
0.8
0.4
0.0
-0.4 -0.2
0.0
0.2
0.4
Gate Bias (V)
0.6
0.0
Current Density (mA/m)
1.6
Gm (mS/m)
Current Density (mA/m)
Lg = 60 nm
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
VDS = 0.1 to 0.7 V
0.2 V increment
SS ~ 80 mV
VDS = 0.1 V
SS ~ 120 mV
VDS = 0.5 V
-0.4 -0.2
0.0
0.2
0.4
Gate Bias (V)
0.6
Current Density (mA/m)
V. Chobpattana et al (Stemmer group),
APPLIED PHYSICS LETTERS 102, 022907 (2013)
2.0
1.6
VGS = -0.4 V to 1.0 V
0.2 V increment
Ron = 268 Ohm-m
1.2 at VGS = 1.0 V
0.8
0.4
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Drain Bias (V)
FinFETs by Atomic Layer Epitaxy: Why ?
Electrostatics:
body must be thinner than ~Lg /2
→ less than 4 nm thick body for 8 nm Lg
Problem:
threshold becomes sensitive to body thickness
3
Vth  Tbody Tbody
Problem:
low mobility unless surfaces are very smooth
6
2
  Tbody
/ Tbody
Implication: At sub-8-nm gate length, need :
atomically-smooth interfaces
atomically-precise control of channel thickness
side benefit: high drive current→ low-voltage, low-power logic
ALE-Defined finFET: Process Flow
Fin template: formed by {110}-facet-selective etch→ atomically smooth
Channel thickness set by ALE growth→ atomically precise
Not shown: gate dielectric, gate metal, S/D metal
HfO2
TiN
channel
10 nm thick fins, 100 nm tall
50 nm fin pitch
fin, ~8nm
100 nm fin pitch
Images
Goal: Tall Fins for High Drive Current
current
fin height
 Jsurface 
transistor width
fin pitch
Goal: fin height >> fin pitch (spacing)→ more current per fin
→ less fins needed → higher integration density
Higher density→ shorter wires→ smaller CwireVdd/I, CwireVdd2/2
7
Is the IC Area Reduction Significant ?
Clock/interconnect drivers need large drive currents.
Area reduction for these is likely substantial.
FETs in Cache Memory & Registers are drawn at minimum width
No area reduction for these.
Most, but not all, Logic Gates will be drawn at minimum width.
Benefit must be evaluated by VLSI architect, not by device physicist.
300 mV Logic: Can We Address The CV2/2 Limit ?
The CV2/2 dissipation limit
1000
60
mV/decade
d
I , A/m
100
Vdd set for target Ion,
hence acceptable CVdd/Ion.
10
Vdd
With minimum Cwire,
a minimum switching
energy CwireVdd2/2 is set
Threshold set for acceptable
off-state dissipation IoffVdd.
1
Cwire
0.1
0
0.1
0.2 0.3 0.4
V
0.5
gs
Subthreshold logic
1000
60
mV/decade
100
d
I , A/m
Tunnel FETs
Vdd is simply reduced.
Decreases energy CVdd2/2.
Increases delay CVdd/Ion.
10
Bandgap of P+ source
truncates thermal distribution.
1
Potential for low Ioff at low Vdd.
0.1
0
0.1
0.2 0.3 0.4
V
gs
0.5
Obtaining high Ion /Vdd is the challenge.
nominal 1mA/micron
@500mV Vdd
60
mV/decade
10000
100
800
600
(a)
10
(b)
400
1
200
d
0.1mA/micron
@ V =0mV
gs
0
0.1
0
0.1
0.2 0.3
V
gs
0.4
0.5
0
0.1
0.2 0.3
V
0.4
0.5
8000
4000
10
4
10
3
10
2
10
1
10
0
(c)
60 mV
dec.
finFET:10:1
height/pitch
6000
0
-0.1 0
0.1 A/m
@ Vgs=0mV
(d)
1000 A/m
@ Vgs=268mV
2000
d
1000
1000
I , Amps per meter of FET footprint width
I , Amps per meter of FET width
Goal: Tall Fins for Low-Power, Low-Voltage Logic
10
0.1 0.2 0.3 0.4 0.5
V
finFET:10:1
height/pitch
-1
-0.1 0
gs
gs
0.1 0.2 0.3 0.4 0.5
V
gs
Supply reduced from 500mV to 268 mV while maintaining high speed.
3.5:1 power savings ? Must consider FET capacitances.
Ctotal  0.2 fF/ m  Lwire
 15  0.3 fF/ m  Wg
 3  I on Lg vinjectionVDD
interconne ct
fringing
gate - channel
 gate  CtotalVDD / 2 I on delay
Esw 
2
CtotalVDD
/2
energy
Assumes (Hodges & Jackson, 2003): (1) Charge-control analysis (2) Ion,PFET / Wg=0.5*Ion,NFET / Wg (3) FO=FI=1
Power and Delay Comparison
I , Amps per meter of FET width
Planar FET, Vdd=500 mV
1000
Ion=20 A, Ioff=2nA
Cg-ch=IonLg /vinjVdd=1.3 aF
nominal 1mA/micron
@500mV Vdd
800
Cgd-f = Cgs-f = 6 aF
600
400
d
200
0
0
0.1
0.2 0.3
V
0.4
0.5
gs
Cwire= 2 fF (10 m length)
Ctotal = 2.1 fF (various multipliers)
delay= 52 ps
Ctotal VDD2= 0.26 fJ
I , Amps per meter of FET footprint width
tall finFET, Vdd=268 mV
10000
8000
60 mV
dec.
finFET:10:1
height/pitch
6000
4000
1000 A/m
@ Vgs=268mV
d
2000
0
-0.1 0
0.1 0.2 0.3 0.4 0.5
V
gs
Ion=20 A, Ioff=2nA
Cg-ch=IonLg /vinjVdd=3.7 aF
Cgd-f = Cgs-f = 60 aF
Cwire= 2 fF (10 m length)
Ctotal = 2.9 fF (various multipliers)
delay= 39 ps
Ctotal VDD2= 0.11 fJ
11
Why tall finFETs ? Why Not Just Subthreshold Logic ?
I , Amps per meter of FET channel width
Planar FET, Vdd=268 mV
Ion=2.0 A
10000
60 mV
dec.
finFET:10:1
height/pitch
8000
6000
1000 A/m
@ Vgs=268mV
4000
2000
d
0
-0.1 0
0.1 0.2 0.3 0.4 0.5
V
gs
I , Amps per meter of FET footprint width
tall finFET, Vdd=268 mV
10000
8000
60 mV
dec.
finFET:10:1
height/pitch
Low Ion→ large CVDD/Ion delay,
subthreshold logic is slow.
Ion=20 A
6000
4000
1000 A/m
@ Vgs=268mV
d
2000
0
-0.1 0
0.1 0.2 0.3 0.4 0.5
V
gs
12
Planar FET, Vdd=268 mV
I , Amps per meter of FET channel width
Why tall finFETs ? Why Not Just Subthreshold Logic ?
Ion=20 A
10000
8000
60 mV
dec.
finFET:10:1
height/pitch
Die size
increased 10:1
6000
4000
1000 A/m
@ Vgs=268mV
2000
(also: longer interconnects, etc)
d
0
-0.1 0
0.1 0.2 0.3 0.4 0.5
V
gs
I , Amps per meter of FET footprint width
tall finFET, Vdd=268 mV
10000
8000
60 mV
dec.
finFET:10:1
height/pitch
Ion=20 A
6000
4000
1000 A/m
@ Vgs=268mV
d
2000
0
-0.1 0
0.1 0.2 0.3 0.4 0.5
V
gs
13
Tunnel FETs & High-Aspect-Ratio Fins
Quick performance estimate:
Assume, for a moment, that P/N tunneling probability is 10%*.
Typical of the best reported ohmic contacts .*
Then on-currents for tunnel FETs are ~10:1 smaller than that of normal FETs.
Unless Ion/Wg is high, tunnel FETs will suffer from either
large CwireV/I gate delays or (increasing FET widths) large die areas.
Using high-aspect ratio fin structures, tunnel FET drive currents can be increased.
Parasitic fringing capacitance will then also contribute to CV/I & CV2.
*Contact to N-InGaAs @ 6E19/cm3 doping: m*=0.1m0, 0.2 eV, 0.5 nm barrier
Baraskar, et al: Journal of Applied Physics, 114, 154516 (2013)
finFETs Defined by Atomic Layer Epitaxy
Fin thickness defined by Atomic layer epitaxy
→ nm thickness control
Fin height defined by sidewall growth
→ 200 nm high fins
InGaAs finFET:
8 nm thick fin
200 nm high
Benefits:
Enables ~4 nm fin bodies→ 8 nm gate length
10:1 more current per unit die area
→ smaller IC die area
Enables high speed, ultra low-power logic,
Vdd~300 mV
D. Elias, DRC 2013, June, Notre Dame
InGaAs NFET
height>> pitch
InGaAs PFET
(end)
Backups
Lithographic Scaling vs. 3-D for High-Density Logic
Past VLSI Scaling: more FETs per IC because of
(1) shorter gate & contact lengths
(2) increased mA/micron→ less gate width Wg.
Today, Ion / Wg (mA/micron) is not increasing
soon, once S/D tunneling dominates, Ion/Wg will start to decrease
Sub-16nm lithography is also difficult.
Further reductions in feature size are expensive.
Can 3-D transistors increase integration density ?
Clear: increased Ion
for a given FET footprint size.
Clear: can suppress S/D tunneling:
tunneling distance >>
lithographic distance.
Less clear: decreased size
of minimum-geometry FET.
18
Scaling in the S/D tunneling limit
At 4-8 nm Gate Lengths,
high leakage from source/drain tunneling

J S / D tunnel  exp  (2m*qVth )1/ 2 Lg / 

increases exponentially as gate length is reduced.
Reducing tunneling through increased mass can be counterproductive
increasing m* → less tunneling, but lower FET on-current→ need more die area
Instead: Ultra-tall fins to increase
the integration density
example: 3-input NOR gate.
other cases: clock & interconnect drivers
19
Minimum gate length: source-drain tunneling (2)
 mA   Vgs  Vth 

  
J  K1   84
 m   1 V 
normalized drive current K
1
0.35
3/ 2
, where K1 
1  (c
100 Silicon
(2 nm well)
InAs (2 nm well)
0.3

g  m* mo

1/ 2
*
dos,o / cequiv )  g  ( m / mo )

3/ 2
g=2
g=1
cequiv  ( 1/cox  1/cinversion_depth )1
0.25
 εSiO 2 /EET
0.2
0.15
0.3 nm
0.1
0.05
EET= (dielectric thickness*SiO2 / oxide )+
(mean wavefunction depth*
0
0.01
analysis: Rodwell et al, 2010 DRC
SiO2
/
semiconductor
0.1
m*/m
)
0.4 nm
0.6 nm
EET=1.0 nm
1
o
increased m* → decreased Ion /Wg → decreases packing density
20
Geometric Solutions to S/D Tunneling
UID InGaAs
vertical spacer
Transport (& tunneling) distance larger than lithographic gate
length.
Feature used NOW in our current planar FETs.
Can be incorporated in high-aspect-ratio finFETs
21
Why Not Release Fins Before S/D Regrowth ?
D. Elias, DRC 2013, June, Notre Dame
Images of released ~10 nm fins:
S/D regrowth provides mechanical support
Wire Lengths & Wire Capacitances in VLSI
logic
gate
FET
gate die area
Integrated Circuit Layout
interconnect
IC area  logic gate area
 transisto r footprint area
mean wire lenght  (transisto r footprint area)1/2
wiring capacitanc e  0.2 fF/ m
mean wirin g capacitanc e
 (transisto r footprint area)1/2
more current per fin→ less fins needed → higher integration density
more current per fin→ shorter wires→ smaller CwireVdd/I, CwireVdd2/2
23
FET Capacitances, Interconnect Capacitances
fringing capacitanc e
C gd , f  C gs, f  0.3 fF/ m Wg
gate - channel capacitanc e
C g ch  I on Lg vinjectionVDD
interconne ct capacitanc e
Cwire  0.2 fF/ m  Lwire
Similar capacitances
in finFET
24
Gate Capacitance, Energy, and Delay
fringing capacitanc e
C gd , f  C gs, f  0.3 fF/ m Wg
gate - channel capacitanc e
C g ch  I on Lg vinjectionVDD
interconne ct capacitanc e
Cwire  0.2 fF/ m  Lwire
Ctotal  0.2 fF/ m  Lwire
 15  0.3 fF/ m  Wg
 3  I on Lg vinjectionVDD

Cto ta lVDD / 2 I o n
2
Esw  Cto ta lVDD
/2
interconnect
fringing
gate - channel
Assumes:
(1) Charge-control analysis*
(2) Ion,PFET / Wg=0.5*Ion,NFET / Wg
(3) FO=FI=1
delay
energy
*Hodges & Jackson, 2003
25