p. 1
Performance Impact of Post-Regrowth
Channel Etching on InGaAs MOSFETs
Having MOCVD Source-Drain Regrowth
Andrew D. Carter1, S. Lee1, D.C. Elias1, C.-Y. Huang1,
J. J. M. Law1, W. J. Mitchell1, B. J. Thibeault1,
V. Chobpattana2, S. Stemmer2,
A. C. Gossard1, and M. J. W. Rodwell1
1ECE
Department, 2Materials Department,
University of California, Santa Barbara, CA 93106
Device Research Conference 2013
Notre Dame, Indiana
6/24/2013
DRC 2013
Overview
p. 2
Why III-V for VLSI?
Device Physics and Scaling
Process Flows
Measurements
Conclusions
DRC 2013
p. 3
Jd,max
Why III V VLSI?
1/Ron
Higher electron velocities than Si MOS
For short Lg FETs,
gm
J drain  q  ns ,channel  vsat
Transconductance, g m  Ceffective  vsat
Jd and gm are key figures of merit in VLSI
However:
Jd and gm degraded by source large Raccess
Jd and gm degraded by interface trap density, Dit
Therefore, we must develop:
Low access resistance source/drain contacts
Thin, high-k, low Dit dielectrics on InGaAs
Fully self-aligned process modules
MOSFETs have been, and always will be, a materials challenge.
DRC 2013
p. 4
FET Device Physics
Cox 
Cdepth 
Cdos
 o r LgWg
tox
 o channel LgWg
tchannel
2
q 2 gm*

LgWg
2
2
nchannel 
Cdos
(Vdos )
q
Dit problem
Cit  q 2 DitWg Lg
↑Cit , ↓ Vsurface
Vsurface supplies Cdos
↓ Vsurface =↓ ndos in Cdos
Electron band diagram: gate-insulator-channel
Candidate III-V Planar Geometries
p. 5
Intel IEDM 2009
“Trench” MOSFET
Leverages HEMT tech.
Gate oxide  Low Ig 
Small footprint 
But
Will the Lg scale?
Replacement Gate MOSFET
Easily defined Lg 
Gate oxide 
Small footprint 
But
Is RG doping high enough?
DRC 2013
p. 6
Gate Replacement FET Process Flow
MBE S/D Regrowth
Nickel Gate Metal
InAs
S/D
100 nm Lg
10 nm Thick Well
Low-damage process
Thermal gate metal
No/Low-damage plasma
Dielectric post-regrowth
InAlAs Back Barrier
STEM FET cross section, color-coded by chemistry
Figure courtesy Jeremy Law (UCSB)
6
DRC 2013
p. 7
Gate Replacement FET Challenges
SEM of dummy gate
MBE regrowth is non-selective  requires photoresist planarization
DRC 2013
Gate Replacement FET Challenges
p. 8
Regrowth
Photoresist
Short dummy gates are hard to planarize, aspect-ratio-limited gate length
DRC 2013
p. 9
Solution: MOCVD S/D Regrowth *
MBE InAs RG
MOCVD InGaAs RG
MBE is non-selective to the SiO2 pillar, while MOCVD is selective!
 PR planarization no longer necessary  short Lg that will not fall over
* Terao et al, APEX 2011, and Egard et al, DRC 2011
DRC 2013
p. 10
MBE Versus MOCVD S/D Regrowth
81 nm Lg, (1 nm Al2O3/ 4 nm HfO2), 10 nm channel, MBE InGaAs Regrowth
0.2 V increment
1.5
1.0
0.5
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Drain Bias (V)
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
32--2012-6-25-15-16--fet_id_vgs_UCSBv9_origin
500
2.0
VDS = 0.1 V, 0.5 V, 0.7 V
SS=194 mV
at VDS=0.1V
100 mV Vds
450
1.5
1.0
0.5
400
SS (mV/dec)
Current Density (mA/m)
VGS = -0.2 V to 0.6 V
10
Gm (mS/m)
Current Density (mA/m)
30--2012-6-25-15-14--fet_id_vds_UCSBv9_origin
2.0
500 mV V
350
ds
300
250
200
150
100
-8
10
-1.0
-0.5
0.0
0.5
0.0
1.0
0.0
0.2
Gate Bias (V)
0.4
0.6
0.8
1.0
Gate Length (micron)
68 Lg, (1 nm Al2O3/ 4 nm HfO2), 10 nm channel, MOCVD InGaAs Regrowth
0.2 V increment
1.5
1.0
0.5
0.0
0.0
result
0.2
0.4
0.6
Drain Bias (V)
0.8
1.0
10
1
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
30--2013-3-3-21-6--fet_id_vgs_ADC01_origin
1600
1550
1500
2.0
VDS = 0.05 V to 0.5 V
1.5
1.0
0.5
50 mV Vds
500 mV Vds
800
600
400
200
-8
10
-1.0
SS (mV/dec)
Current Density (mA/m)
VGS = -0.6 V to 0.6 V
10
Gm (mS/m)
Current Density (mA/m)
31--2013-3-3-21-8--fet_id_vds_ADC01_origin
2.0
-0.5
0.0
0.5
0.0
1.0
Gate Bias (V)
Similar on-state performance, but large Vth shift, poor SS, DIBL
0.0
0.2
0.4
0.6
0.8
1.0
Gate Length (micron)
DRC 2013
p. 11
Poor subthreshold: Channel Degradation
> 300 mV/dec subthreshold swing  Dit ? Channel degradation?
Experiment: SiO2 capping + high temp anneal + strip  MOSCAP 5 nm Al2O3
o
SiO Capped, 500 C anneal
Control
2
1.2
1 KHz
10 KHz
100 KHz
1 MHz
Capacitance (F/cm2)
1
Large dispersion
 Large Dit
0.8
0.6
0.4
0.2
0
-2
-1
0
Voltage (V)
1
2
-2
-1
0
1
Voltage (V)
2
InP channel capping for RG  large subthreshold swing for FETs 
DRC 2013
MOCVD: Digital Channel Etching
p. 12
Digital semiconductor etching*
Before ALD deposition:
Oxidize channel surface (UV O3)
Etch oxide in HCl:DI
Repeat as needed
Etches ~ 1.2 nm per cycle
Top-down thin channels  Increase Cdepth
Simultaneous damage removal and body scaling
* S.Lee et al, IPRM 2013
DRC 2013
MOCVD RG with Digital Channel Etching
68 nm actual Lg, (1 nm Al2O3/ 4 nm HfO2), No digital etching (~ 10 nm channel)
Current Density (mA/m)
VGS = -0.6 V to 0.6 V
0.2 V increment
1.5
1.0
0.5
0.0
0.0
0.2
0.4
0.6
0.8
1.0
10
10
1
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
30--2013-3-3-21-6--fet_id_vgs_ADC01_origin
2.0
VDS = 0.05 V to 0.5 V
0.45 V increment
1.5
1.0
0.5
-8
10
-1.0
Drain Bias (V)
-0.5
0.0
0.5
Gm (mS/m)
Current Density (mA/m)
31--2013-3-3-21-8--fet_id_vds_ADC01_origin
2.0
0.0
1.0
Gate Bias (V)
65 nm actual Lg, (1 nm Al2O3/ 4 nm HfO2) 2 cycles of digital etching (~ 6.5 nm channel)
result
Current Density (mA/m)
VGS = 0 V to 1.2 V
0.2 V increment
1.5
1.0
0.5
0.0
0.0
0.2
0.4
0.6
Drain Bias (V)
0.8
1.0
10
10
1
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
91--2013-3-2-12-28--fet_id_vgs_ADC01_origin
2.0
VDS = 0.05 V to 0.5 V
0.45 V increment
SS=186 mV
at VDS= 50 mV
1.5
1.0
0.5
-8
10
-1.0
-0.5
0.0
0.5
Gm (mS/m)
Current Density (mA/m)
67--2013-3-3-22-3--fet_id_vds_ADC01b_origin
2.0
0.0
1.0
Gate Bias (V)
All devices improve with channel etch  thinner channel, remove surface damage
p. 13
p. 14
MOCVD RG with Digital Channel Etching
Peak transconductance (mS/micron):
50 nm as drawn gate length, 0.5 V Vgs
2 Cycle Etching
(~6.5 nm ch.)
gm map
map nm ch.)
No Etchinggm(10
1.10
0.90
1
0.89
0.92
1.00
2
1.50
1.50
1.45
1.51
1.50
1.21
1.53
1.53
1.38
Blank
1.45
1.53
1.48
1.15
1.58
1.42
1.36
1.26
1.47
1.09
1.38
1.42
1.47
1.39
1.50
A
B
C
D
E
F
2
0.93
0.90
1.10
3
3
1.01
Blank
1.09
0.91
1.16
4
4
Open
1.01
1.11
1.03
0.92
1.05
5
5
0.99
1.00
0.96
Open
0.88
Open
6
6
A
result
1.38
1
B
C
D
E
F
All devices improve with channel etch  thinner channel, remove surface damage
MOCVD RG with Digital Channel Etching
result
All devices improve with channel etch  thinner channel, remove surface damage
p. 15
MOCVD RG with Digital Channel Etching
result
Lower performance for not etched channels not due to metal-RG contact
p. 16
DRC 2013
p. 17
MOCVD RG: Recent Results
48 nm gate length, ~ 3.8 nm HfO2, InGaAs with 2 cycle digital etching, p-doped back barrier
0.2 V increment
1.5
Ron = 229 ohm - m
1.0
0.5
0.0
0.0
0.1
0.2
0.3
0.4
0.5
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
210--2013-4-3-15-16--fet_id_vgs_ADC01_origin
VDS = 0.05 V to 0.5 V
0.45 V increment
SS=158 mV
at VDS= 50 mV
2.0
2.0
1.5
1.0
0.5
gm (mS/micron)
Current Density (mA/m)
VGS = 0 V to 1.2 V
10
Gm (mS/m)
Current Density (mA/m)
212--2013-4-3-15-28--fet_id_vds_ADC01b_origin
2.0
1.5
1.0
0.5
0.0
-8
10
-1.0
-0.5
0.0
0.0
1.0
0.5
Gate Bias (V)
Drain Bias (V)
0.0 0.2 0.4 0.6 0.8 1.0
Gate Length (micron)
Drain Bias (V)
* S. Lee et al, VLSI 2013
Current Density (mA/m)
2.2
2.0 VGS = -0.4 V to 1.4 V
1.8
0.2 V increment
1.6 R = 214 Ohm-m
on
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.1
0.2
0.3
0.4
0.5
1.8
2.8
40 nm
70 nm
90 nm
1.6
1.4
2.4
2.0
1.2
1.0
1.6
0.8
1.2
0.6
0.8
0.4
0.2
0.0
VDS = 0.5 V
-0.2
0.0
0.2
0.4
0.6
0.4
0.0
Ni
Gm (mS/m)
Current Density (mA/m)
40 nm gate length, ~ 3.6 nm HfO2 , InAs/InGaAs channel, digitally etched *
3.6 nm HfO2
0.5 nm Interfacial layer
60 nm
5 nm InAs
3 nm In0.53GaAs
Lg ~40 nm
In0.52AlAs
Gate Bias (V)
High performance III-V MOS using aggressively scaled ALD dielectrics
Conclusions
p. 18
65 nm gate last InGaAs MOSFET process flow using MOCVD
Jdrain = 0.78 mA/m at 0.5 V Vgs – Vth , 0.5 V Vds
Peak transconductance: 1.58 mS/micron at 0.5 V Vds
Self-aligned process path for sub-50 nm III-V VLSI
Continued research areas
Thinner gate dielectrics
Body scaling (thin planar QW and/or FinFETs)
Improved Dit passivation techniques
DRC 2013
p. 19
Thanks for your time!
Questions?
contact address: adc [at] ece.ucsb.edu
This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.009).
A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and
MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.
DRC 2013
p. 20
BACK UP SLIDES
DRC 2013
Source-Drain Regrowth Data
p. 21
DRC 2013
p. 22
MOCVD RG: Recent Results
48 nm gate length, ~ 3.8 nm HfO2, InGaAs with 2 cycle digital etching, p-doped back barrier
0.2 V increment
1.5
1.0
0.5
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
210--2013-4-3-15-16--fet_id_vgs_ADC01_origin
VDS = 0.05 V to 0.5 V
0.45 V increment
SS=158 mV
at VDS= 50 mV
2.0
2.0
1.5
1.0
0.5
gm (mS/micron)
Current Density (mA/m)
VGS = 0 V to 1.2 V
10
Gm (mS/m)
Current Density (mA/m)
212--2013-4-3-15-28--fet_id_vds_ADC01b_origin
2.0
1.5
1.0
0.5
0.0
-8
10
-1.0
-0.5
0.0
0.0
1.0
0.5
Gate Bias (V)
Drain Bias (V)
0.0 0.2 0.4 0.6 0.8 1.0
Gate Length (micron)
Drain Bias (V)
* S. Lee et al, VLSI 2013
Current Density (mA/m)
2.2
2.0 VGS = -0.4 V to 1.4 V
1.8
0.2 V increment
1.6 R = 214 Ohm-m
on
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.1
0.2
0.3
0.4
0.5
1.8
2.8
40 nm
70 nm
90 nm
1.6
1.4
2.4
2.0
1.2
1.0
1.6
0.8
1.2
0.6
0.8
0.4
0.2
0.0
VDS = 0.5 V
-0.2
0.0
0.2
0.4
0.6
0.4
0.0
Ni
Gm (mS/m)
Current Density (mA/m)
40 nm gate length, ~ 3.6 nm HfO2 , InAs/InGaAs channel, digitally etched *
3.6 nm HfO2
0.5 nm Interfacial layer
60 nm
5 nm InAs
3 nm In0.53GaAs
Lg ~40 nm
In0.52AlAs
Gate Bias (V)
High performance III-V MOS using aggressively scaled ALD dielectrics
FET Device Physics
Cox 
Cdepth 
Cdos, 2 D
nchannel 
p. 23
 o r
tox
 o channel
tchannel
2
q 2 gm*

 2
Cdos
(Vdos )
q
J drain  q  ns ,channel  vsat
g m  Ceffective  vsat
*Ceffective includes Cox, Cdepth, Cdos
Electron band diagram of a quantum well FET
DRC 2013
WS/D
FET Device Scaling
p. 24
Lg
Contacted Gate Pitch
LS/D
Lg
LS/D
Rsh Lgap
1)
Si CMOS scaling:Rmeasured
Contacted
 gate pitch
 2 R4x
c the gate length
4:1 reduction of contact
W
area2)
rc
 4:1 reduction of rcontact
Rcnm
 L forFor
L
1.5=LTL , requires 5x10-9 ohm-cm2 r
22 nm node  33
L
S/D
T
contact
LS/D
W
T
Contact Transfer Length  LT 
1)
2)
S. Natarajan, et al, IEDM 2008.
M.J.W. Rodwell, et al, IPRM 2010.
rc
Rsh
DRC 2013
Gate First FET Process Flow
p. 25
Thick (10 nm) channel
Process damage mitigation
Heavy ( ~ 9x1012 cm-2) d doping
Prevents ungated sidewall current choke
In0.52Al0.48As heterobarrier
Carrier confinement
Semi-insulating InP
Device isolation
DRC 2013
Gate First FET Process Flow
p. 26
Front End: Gate Stack Definition
In-situ hydrogen plasma / TMA treatment before Al2O3 growth
Mixed e-beam / optical lithography
Bi-layer gate (Sputtered W + e-beam evaporated Cr)
High selectivity, low power dry etch
DRC 2013
p. 27
FET Process Development
Use optical lithography to produce >0.5um gates
Use electron beam lithography to produce sub-100nm gates
Need to investigate possible e-beam damage to oxides
HSQ (SiO2)
SiO2 +
SiNx
Cr
Cr
Field: SiNx
Cr +
SiNx
SiO2
W+
SiNx
W
EBL Tests
Finished Gate Etch + Sidewall Deposition
DRC 2013
p. 28
FET Process Development
ICP dry etches calibrated to perform at sub-100nm scale
HSQ
Cr
SiO2
HSQ
Increased
ICP Power
Cr
SiO2
Cr
Cr
W
W
Higher power dry etch  vertical gate stack
Undercutting leads to fallen gates, ungated access regions
 Minimize Cr undercut by reducing thickness
DRC 2013
Gate First FET Process Flow
p. 29
Front End: Gate Stack Definition
Sidewall Deposition
Conformal, protects S/D short circuit to gate
Sidewall etch
Vertical gate stack  self aligned sidewall
DRC 2013
FET Process Development
p. 30
Low power etch  Isotropic etching + undercut  fallen gates
Large undercuts  ungated regions  high Raccess
Thick gate stack:
Small Lg 
Large sidewall foot 
Unreliable gates 
Thin Cr stack:
Small
Lg 
Large
sidewall foot 
Repeatable gate etch?
ALD SiO2 sidewall:
Small Lg 
Still sidewall foot! 
Unrepeatable gate undercut

DRC 2013
Gate First FET Process Flow
p. 31
Regrowth and Back End
Surface preparation
UV O3 exposure to clean the source/drain, removed ex-situ before MBE load
MBE InAs Regrowth
Low arsenic flux, high temperature  near gate fill in
Metallization and Mesa Isolation
In-situ Mo in MBE optional for lower rc
Ti/Pd/Au liftoff
Wet etch for mesa isolation
DRC 2013
p. 32
Gate First FET Process Flow
SiO2
Chrome
Tungsten
Regrowth
Regrowth
TEM micrographs of 60 nm Lg device
SiNx Sidewalls
DRC 2013
p. 33
Gate First FET Results
60 nm Lg
115 nm Lg
Increased leakage current:
Heavy d doping leakage path
Drain induced barrier lowering
DRC 2013
Gate First FET Results
p. 34
60 nm Lg
1/Ron
High Jdrain but depletion mode
Transconductance: Similar to previous results* (~0.3mS/m)
Low Ron (371 ohm-m) for InGaAs MOSFETs
*) U.
Singisetti et al, IEEE EDL Nov. 2009.
DRC 2013
p. 35
Gate First FET Results
Wg = 9 m
Jdrain increases rapidly with gate length scaling
Transconductance: Relatively flat with gate length scaling
*) U.
Singisetti et al, IEEE EDL Nov. 2009.
DRC 2013
p. 36
FET: Access Resistance
2000
2000
2
y = 400.46 + 795.01x R = 0.98313
2
y = 193.37 + 818.63x R = 0.9865
2
W g=25 m
Tchan=15 nm
2
y = 304.7 + 608.65x R = 0.98906
1500
Resistance (ohm-m)
On Resistance (ohm-mm)
y = 337.87 + 658.51x R = 0.9877
W g=9 m
Tchan=10 nm
1000
500
V = 1V
gs
1500
1000
500
V = 2V
gs
V = 3V
gs
0
0
0
0.2
0.4
0.6
0.8
1
1.2
0
1.4
Gate Length (m)
Raccess:
200 ohm-m
0.2
0.4
0.6
0.8
1
1.2
1.4
Gate Length (m)
Rmeasured 
MOSFET On Resistance
Rsh Lgap
W
 2 Raccess
Raccess:
100 ohm-m
Gateless Transistor Resistance
Gateless transistor effective diagnostic of regrowth
DRC 2013
p. 37
Gate First FET: Metal-Regrowth TLM
Wg = 14 m
Rmeasured 
Rc 
LT 
rc
LT W
Rsh Lgap
W
 2 Rc
for L  1.5LT
rc
Rsh
Metal-Regrowth access resistance
is not a limiting factor in Jdrain
Ex-situ Ti/Pd/Au / n-type InAs contacts: rc = 2 x 10-8 ohm-cm2
In-situ Mo / n-type InAs contacts have shown rc = 6 x 10-9 ohm-cm2
*)
M.J.W. Rodwell, et al, IPRM 2010.
*
DRC 2013
Gate First FET: Issues
p. 38
Ungated region  potential current choke
Thinner sidewall can help…
… but hard to control with gate undercut
Electron band diagram of channel underneath sidewall
DRC 2013
p. 39
Gate First FET: Issues
Heavy d doping  parallel conduction, poor gm
Large leakage current in device
Decreases Cdepth  limits gm
9  1012 cm2 d doping
no d doping
Must reduce d doping while maintaining low Raccess
DRC 2013
p. 40
FET Device Physics
Cox 
Cdepth 
Cdos
 o r LgWg
tox
 o channel LgWg
tchannel
2
q 2 gm*

LgWg
 2
nchannel
C
 dos (Vdos )
q
Cit  q 2 DitWg Lg
• Dit problem
– ↑Cit , ↓ Vsurface
– Vsurface also supplies
Cdos
– ↓ Vsurface =↓ ndos in Cdos
DRC 2013
p. 41
FET Device Scaling
FET parameters
Scaling Rule
How?
Current Density (mA / m) , gm (mS / m)
increase 2:1
Gate Length and Contact Spacing (Lg,LS/D)
decrease 2:1
Lithographic Scaling
Channel Electron Density
increase 2:1
Channel Material and Orientation
constant
Channel Material and Orientation
Electron Transport Mass (m*transverse )
Gate Capacitance
increase 2:1
Channel Density of States
increase 2:1
Channel Material and Orientation
Channel Thickness (Tinv)
decrease 2:1
Materials Engineering
Effective Oxide Thickness (Tox)
decrease 2:1
Materials Engineering
decrease 4:1
Materials Engineering
Source/Drain Contact Resistivity
Rodwell, IPRM 2010
DRC 2013
WS/D
FET Device Scaling
p. 42
Lg
Contacted Gate Pitch
LS/D
Rmeasured 
Rsh Lgap
W
 2 Rc
- 5 nm channel, 500 cm2/(V*s) mobility, 5E19 cm-3 carriers = 500 ohm/sq
r
2 contact
c resistance
- 5E-9 ohmRcm
for L  1.5L
c
- Ltransfer ~ 31 nm
LTW
T
Contact Transfer Length  LT 
1)
2)
S. Natarajan, et al, IEDM 2008.
M.J.W. Rodwell, et al, IPRM 2010.
rc
Rsh
DRC 2013
p. 43
FET Process Development
1) Poorly controlled dry etch undercut
– Low power etch  Isotropic etching
Thick gate stack:
Small Lg 
Large sidewall foot 
unreliable gates 
Thin Cr stack:
Small Lg 
Large sidewall foot 
Reliable gate etch?
ALD SiO2 sidewall:
Small Lg 
Still sidewall foot! 
Unreliable gate undercut

DRC 2013