2010 IEEE Device Research Conference, June 21-23, Notre Dame, Indiana
III-V FET Channel Designs
for High Current Densities
and Thin Inversion Layers
Mark Rodwell
University of California, Santa Barbara
Coauthors:
W. Frensley:
University of Texas, Dallas
S. Steiger, S. Lee, Y. Tan, G. Hegde, G. Klimek
Network for Computational Nanotechnology, Purdue University
E. Chagarov, L. Wang, P. Asbeck, A. Kummel,
University of California, San Diego
T. Boykin
University of Alabama, Huntsville
J. N. Schulman
The Aerospace Corporation, El Segundo, CA.
Acknowledgements:
Herb Kroemer (UCSB), Bobby Brar (Teledyne)
Art Gossard (UCSB), John Albrecht (DARPA)
rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax
Thin, high current density III-V FET channels
InGaAs, InAs FETs
THz & VLSI need high current
low m*→ high velocities
FET scaling for speed requires increased charge density
low m* →low charge density
Density of states bottleneck (Solomon & Laux IEDM 2001)
→ For < 0.6 nm EOT, silicon beats III-Vs
Open the bottle !
low transport mass → high vcarrier
multiple valleys or anistropic valleys → high DOS
Use the L valleys.
Simple FET Scaling
Goal: double transistor bandwidth when used in any circuit
→ reduce 2:1 all capacitances and all transport delays
→ keep constant all resistances, voltages, currents
gate-source, gate-drain
fringing capacitances:
0.15-0.25 fF/mm
C gd / Wg ~ 
must increase gate
capacitance/area
g m / Wg ~ v  (C gs / LgWg )
Cgs / Wg  (Cgs / Wg Lg )  Lg
C gs, f / Wg ~ 
must reduce
gate length
To double speed, we must double ( g m / Wg ) , ( I D / Wg ), (C gs / LgWg ), ns .
FET Scaling Laws
LG
Changes required to double device / circuit bandwidth.
laws in constant-voltage limit:
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
electron mass in transport direction
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
Current densities should double
Charge densities must double
change
decrease 2:1
increase 2:1
increase 2:1
constant
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
gate width WG 
Semiconductor Capacitances Must Also Scale
(Vgs  Vth )
( unidirecti onal motion)
cox
cdepth   / Tinversion
( E f  Ewell ) / q
cdos  q 2 gm* / 2 2
channel charge  qns  cdos (V f  Vwell )  q( E f  Ewell )  ( gm* / 22 )
Inversion thickness & density of states must also both scale.
Calculating Current: Ballistic Limit
Natori
Channel Fermi voltage  voltage applied to cdos
determines Fermi velocity v f through E f  qV f  m * v 2f / 2
mean electron velocity  v  ( 4 / 3 )v f
Channel charge : s  cdos V f  Vc  
cdoscequiv
cequiv  cdos
V
gs
 Vth 
cdos  q2 gm * / 22  cdos,o  g  (m * / mo ) , where g is the # of band minima
 mA 
 Vgs  Vth 
g  (m * / mo )1 / 2
 J   84

3/ 2 
 1 V 
m
m


1

(
c
/
c
)

g

(
m
*
/
m
)




dos,o
ox
o
3/ 2
Do we get highest current with high or low mass ?
Drive current versus mass, # valleys, and EOT
 mA   Vgs  Vth 

  
J  K1   84
 mm   1 V 
normalized drive current K
1
0.35
3/ 2
, where K1 
InGaAs <--> InP
1  (c

g  m* mo
1/ 2
*
dos,o / cequiv )  g  ( m / mo )
Si

3/ 2
g=2
g=1
0.3
cequiv  ( 1/cox  1/cdepth )1
0.25
 εSiO2 /EOT
0.2
0.3 nm
0.4 nm
0.15
0.1
0.05

0.6 nm
EOT includes the wavefunction depth term
(mean wavefunction depth* SiO2 /semiconductor )
0
0.01
EOT=1.0 nm
0.1
m*/m
1
o
InGaAs MOSFETs: superior Id to Si at large EOT.
InGaAs MOSFETs: inferior Id to Si at small EOT.
Solomon / Laux Density-of-States-Bottleneck → III-V loses to Si.
Transit delay versus mass, # valleys, and EOT
1/ 2
Lg
 m* 

  1 Volt 
Qch
 
 ch 
 K 2  
where K 2   
7


ID
 2.52 10 cm/s   Vgs  Vth 
 m0 
1/ 2
EOT=1.0 nm
1.5
0.6 nm
1 nm
0.4 nm
0.6 nm
0.4 nm
2
Normalized transit delay K
1/ 2
* 
 cdos,o
m
 1 
g 

ceq
mo 

1
cequiv  ( 1/cox  1/csemi )1
 εSiO2 /EOT
g=1, isotropic bands
0.5
g=2, isotropic bands
EOT includes wavefunction depth term
(mean wavefunction depth*SiO2 /semiconductor )
0
0
0.05
0.1
0.15
0.2
0.25
m*/m
0.3
0.35
o
Low m* gives lowest transit time, lowest Cgs at any EOT.
0.4
Low effective mass also impairs vertical scaling
Shallow electron distribution needed
for high Id, high gm / Gds ratio,
low drain-induced barrier lowering.
2
* 2
Energy of Lth well state  L / m Twell .
For thin wells,
only 1st state can be populated.
For very thin wells,
1st state approaches L-valley.
Only one vertical state in well.
Minimum ~ 3 nm well thickness.
→ Hard to scale below 10-16 nm Lg.
III-V Band Properties, normal {100} Wafer

L
X
 valley
material
substrate m* / mo
material
substrate
0.045
In 0.5Ga 0.5As InP
0.026
InAs
InP
0.067
GaAs
GaAs
--Si
Si
ml / mo
X valley
mt / mo
E x  E
ml / mo
L valley
mt / mo
E L  E
1.29
1.13
0.19
0.16
0.83 eV
0.87 eV
1.30
0.92
0.22
0.19
0.47 eV
(negative)
1.23
0.65
1.90
0.062
0.050
0.075
L - valley tra nsverse masses are comparable to  valleys
0.47 eV
0.57 eV
0.28 eV
Consider instead: valleys in {111} Wafer

L
X
 valley
material
substrate m* / mo
material
substrate
0.045
In 0.5Ga 0.5As InP
0.026
InAs
InP
0.067
GaAs
GaAs
--Si
Si
ml / mo
X valley
mt / mo
E x  E
ml / mo
L valley
mt / mo
E L  E
1.29
1.13
0.19
0.16
0.83 eV
0.87 eV
1.30
0.92
0.22
0.19
0.47 eV
(negative)
1.23
0.65
1.90
0.062
0.050
0.075
Orientatio n : one L valley has high vertical mass
X valleys & three L valleys have moderate vertical mass
0.47 eV
0.57 eV
0.28 eV
Valley in {111} wafer: with quantization in thin wells

L
X
 valley
material
substrate m* / mo
material
substrate
0.045
In 0.5Ga 0.5As InP
0.026
InAs
InP
0.067
GaAs
GaAs
--Si
Si
ml / mo
X valley
mt / mo
E x  E
ml / mo
L valley
mt / mo
E L  E
1.29
1.13
0.19
0.16
0.83 eV
0.87 eV
1.30
0.92
0.22
0.19
0.47 eV
(negative)
1.23
0.65
1.90
0.062
0.050
0.075
Selects L[111] valley; low transv erse mass
0.47 eV
0.57 eV
0.28 eV
{111}
-L FET: Candidate Channel Materials
 valley
material
material
In
material
0.5 Ga
0.5 As
In
Ga
0.5
0.5 As
GaAs
GaAs
GaSb
GaSb
Ge
valley
LLvalley
/m
mm
t /t mo o
0.062
0.062
0.075
0.075
/m
m* / mo mm
l /l mo o
1.23
0.045 1.23
1.90
0.067 1.90
1.30
0.10
0.10
0.039 1.30
1.58
0.08
Well thickness for
EEL LEE 
  L alignment
0.47eV
eV
0.47
1 nm (?)
0.28eV
eV
0.28
2 nm
0.07eV
eV
0.07
4 nm
(negative) - - -
=0 eV
L=177 meV
X[100]= 264 meV
X[010] = 337 meV
Wavefunctions
3 nm GaAs well
AlSb barriers
Energy, eV
Standard III-V FET:  valley in [100] orientation
2
1.5
1
0.5
0
-0.5
-1


-1
X[010]
X[100]
L

L
1st Approach: Use both  and L valleys in [111]
2.3 nm GaAs well
AlSb barriers
[111] orientation
-1
X
L[111]
L[111]

L[111]
= 41 meV
L[111] (1)= 0 meV
L[111] (2)= 84 meV
L[111] , etc. =175 meV
X=288 meV
-1
L[111]

Combined -L wells in {111} orientation vs. Si
 mA   Vgs  Vth 

  
J  K1   84
 mm   1 V 
0.35
, where K1 
GaSb GaAs
1  (c
g  m mo
*

1/ 2
/ cequiv )  g  (m / mo )
*
dos,o
Si
1
Normalized current density K

3/ 2
g=2
0.3
cequiv  ( 1/cox  1/csemi )1
 εSiO2 /EOT
0.25
0.2
0.3 nm
0.15
0.4 nm
0.1

3/ 2
combined ( -L) transport
0.6 nm
0.05 EOT includes the wavefunction depth term
(mean wavefunction depth*SiO2 /semiconductor )
0
0.01
EOT=1.0 nm
0.1
m*/m
o
2 nm GaAs  /L well→ g =2, m*/m0=0.07
4 nm GaSb  /L well→ m*/m0=0.039, mL,t*/m0=0.1
1
2nd Approach: Use L valleys in Stacked Wells
Three 0.66 nm GaAs wells
0.66 nm AlSb barriers
[111] orientation
L[111](1) = 0 meV
L[111](2)= 61 meV
L[111](3)= 99 meV
=338 meV
L[111], etc =232 meV
X=284 meV

X
L[111]
L[111]
-1
All
L[111]
-1
Increase in Cdos with 2 and 3 wells
3
C
dos,N-well
/C
dos,1-well
3 wells
2.5
2
2 wells
1.5
1
0.01
1 nm well pitch
2 nm well pitch
3 nm well pitch
0.1
m*/m
1
o
3 High Current Density (111) GaAs/AlSb Designs
(100) orientation
(111) orientation
2.3 nm GaAs well
AlSb barriers
2
1.5
1
0.5
0
-0.5
-1
Charge density, 1/cm
3
Wavefunctions
Energy, eV
3 nm GaAs well
AlSb barriers

X[010]
X[100]
L

L
2
s
X
L[111]
L[111]

L[111]
-1
Three 0.66 nm GaAs wells
0.66 nm AlSb barriers

X
L[111]
L[111]
X
L[111]
L[111]
L[111]
-1
-1

All
L[111]
both L[111]
-1
20
1 10
19
8 10
19
6 10
19
4 10
19
2 10
0
0 10
L[111]

-1
-1
-1
-1
0 1 2 3 4 5 6 7
position, nm
0 1 2 3 4 5 6 7
position, nm
12
N (1/cm )
Two 0.66 nm GaAs wells
0.66 nm AlSb barriers
8 10
12
6 10
4 10
12
2 10
12
0
-1
0 1 2 3 4 5 6 7
position, nm
0 1 2 3 4 5 6 7
position, nm
L valleys filling
0
0
0
-0.2 -0.1 0 0.1 0.2 0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.2 -0.1 0 0.1 0.2 0.3
(V -V ), V
(V -V ), V
(V -V ), V
(V -V ), V
gs th
gs
th
gs
th
gs
th
Concerns
Nonparabolic bands reduce bound state energies
Failure of effective mass approximation:1-2 nm wells
1-2 monolayer fluctuations in growth
→ scattering→ collapse in mobility
Purdue Confirmation
Purdue Confirmation
Steiger, Klimeck, Boykin
Ryu, Lee, Hegde, Tan
1-D FET array = 2-D FET with high transverse mass
2-D FET
1-D Array FET
Weak coupling → narrow transverse-mode energy distribution→ high density of states
3rd Approach: High Current Density L-Valley MQW FINFETs
8
2.5 nm well pitch
Drain current, mA/mm
7
6
V -V =0.3 V
gs
5
3
5 nm well pitch
2
1 EOT includes wavefunction depth term
0
0.01
 2 2 2
i
2m*W 2
th
4
(mean wavefunction depth*
valley energies Emin, i  qVmin, i 
0.3 nm EOT
0.6 nm EOT
current I  
i
SiO2
/
0.1
m*/mo
semiconductor
)
1
gq 2
V f  Vmin,i  charge : Qch   gl  2m*qV f  Vmin,i  gate voltage :Vgs  V f  Qch / Cox

i
4th Approach: {110} Orientation→ Anisotropic Bands
P. Asbeck
transport
L [111], L[11 1 ] : moderate vertical mass  valleys populate
High in - plane mass perpendicu lar to transport  high density of states
Low in - plane mass parallel to transport  high carrier ve locity
L [1 1 1], [ 1 11] : low vertical mass  depopulate
High in - plane mass parallel to transport  low carrier ve locity
Challenge : only moderate energy separation between desired and undesired valleys.
Anisotropic bands, e.g. {110}
 mA   Vgs  Vth 

  
J  K1   84
 mm   1 V 
3/ 2
, where K1 
0.6
1
normalized drive current K
g=2, m
1/ 2
||
/ mo )

3/ 2
0
/m =0.5
perpendicular
0
cequiv  ( 1/cox  1/csemi )1
 εSiO2 /EOT
0.3
Transport in {110}
oriented L valleys
EOT=1.0 nm
0.2
0.1
/ cequiv )  g  (m m
perpendicular
0.6 nm
0.4
dos,o
1/ 2

g=2, m
/m =0.7
perpendicular
0
g=2, m
/m =0.6
0.3 nm
0.4 nm
0.5
1  (c
g  (m1/ 2 / mo1/ 2 )
EOT includes wavefunction depth term
(mean wavefunction depth*
/
0
0.01
SiO2
semiconductor
)
0.1
m*/m
1
o
GaAs and Ge {110} MOSFETs with L - valley tra nsport
GaAs : n  2, m t / mo  0.075, ml / mo  1.9
Ge : n  2, m t / mo  0.081, ml / mo  1.58
THz FET scaling: with & without increased DOS
Gate length
nm
Gate barrier EOT nm
well thickness
nm
S/D resistance
effective mass
# band minima
canonical
fixed DOS
stepped #
50
1.2
8.0
Wmm 210
*m0
0.05
1
1
1
35
0.83
5.7
25
0.58
4.0
18
0.41
2.8
150
0.05
100
0.05
74
0.08
1.4
1
1
2
1
1
2.8
1
2
13
0.29
2.0
53
9
0.21
1.4
37
0.08
0.08
4
1
3
5.7
1
3
3000
f
2000
4000
2500
max
1500
3500
3000
fmax
2000
f

f , GHz
2500
canonical scaling
stepped # of bands
 transport only
, GHz
Scaled FET performance: fixed vs. increasing DOS
1500
1000
500
500
0
2.5
0
1000
SCFL static divider clock rate, GHz
drain current density, mA/mm
1000
mA/mm→ VLSI metric
2
1.5
1
0.5
200 mV gate overdrive
0
0
10
20
30
40
gate length, nm
50
60
SCFL divider speed
800
600
400
200
0
0
10
20
30
40
gate length, nm
50
Increased density of states needed for high drive current, fast logic @ 16, 11, 8 nm nodes
60
10 nm / 3 THz III-V FETs: Challenges & Solutions
gate dielectric:
decrease EOT 2:1
To double the bandwidth:
S/D access regions:
decrease resistivity 2:1
S/D regrowth
Wistey et al
Singisetti et al
channel: keep same velocity, but
thin channel 2:1
increase density of states 2:1
L
(end)
Purdue Confirmation
MOSFET Scaling Laws
parameter
gate length Lg , source-drain contact lengths
Constant - voltage / constant - velocity scaling laws :
Changes required for  : 1 increased bandwidth in an arbitrary circuit
law
 1
parameter
gate-channel capacitance C g ch
law
 1
 [1 / Cox  1 / Csemi  1 / C DOS ]1 (fF)
LS / D (nm)
 1
transconductance g m ~ C g  ch v injection / Lg (mS)
0
equivalent oxide thickness Teq  Tox SiO /  oxide
 1
 1
(nm)
dielectric capacitance Cox   SiO LgWg / Teq (fF)
gate-source, gate-drain fringing capacitances
C gs, f  Wg , C g d  Wg (fF)
 1
S/D access resistances Rs , R d ( W )
0
S/D contact resistivity Rs / Wg , Rd / Wg ( W  mm )
 1
gate width W g (nm)
2
2
inversion thickness Tinv ~ Twell / 2 (nm)
 1
S/D contact resistivity  c ( W  mm 2 )
 2
semiconductor capacitance
Csemi   semi LgWg / Tinv (fF)
 1
drain current I d ~ g m (V g s  Vth ) (mA)
0
DOS capacitance CDOS  q 2 nm* LgWg / 2 2 (fF)
 1
drain current density ( mA/mm )
1
electron density n s ( cm-2 )
1
temperature rise (one device, K)
~ Wg1
2.0 nm GaAs well, AlAs barriers, on {111} GaAs
Bound state energy, eV
1.2
1
 valley
0.8
0.6
0.4
L(l) valley
0.2
0
-10
10
-9
10
well thickness, meters
10
-8
2 nm well :  and L(l) minima both populated.
 : m * / mo  0.067
*
L( l) : mlateral
/ mo  0.075
low m*  high carrier ve locity
two band minima  doubles cdos
2 nm well  good electrosta tics at ~ 5 - 7 nm Lg .
GaSb well, AlSb barriers, on {110} GaSb
GaSb well, AlSb barriers, on (110) GaSb
Bound state energy, eV
0.6
0.5
L [111],
L[11-1]
0.4
X [100],
X[010]

X [001]
0.3
L [1-11],
L[-111]
0.2
0.1
0
-10
10
-9
10
well thickness, meters
10
-8