2002 ECOC Conference, September, Copenhagen
50-200 GHz InP HBT Integrated Circuits
for Optical Fiber and mm-Wave
Communications
Mark Rodwell
University of California, Santa Barbara
rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax
Electronics for GigaHertz Commun
Applications: optical fiber transceivers at 40 Gb/s and higher
Wideband Optical Transceiver
Key advantages for:
TIA, LIA, Modulator driver
addr
dete
O/E, E/O interfaces
A
DMUX
D
Losing competition with SiGe:
MUX/CMU, DMUX/CDR
excessive power
problems with integration scale
PLL
rout
clock
MUX
Wideband mm-Wave Transceiver
mm-wave interfaces
80 & 160 Gb may come in time
world may not need capacity for some time
WDM might be better use of fiber bandwidth
I
Q
A
D
PLL
DMUX
I
Q
A
DMUX
D
power
amplifier
D
I
Q
A
I
MUX
D
A
Q
This presentation: how InP HBT ICs will be able to do 160 Gb/s
"If you build it, they will come." (today, this argument is not convincing).
S
n
d
o
mmWave Transmission
UCSB
1
(Weather permitting)
1 km
Sea level
0.1
Log Transmission
Atmospheric attenuation is LOW
(~4 dB/km) at bands of interest
60-80 GHz, 120-160 GHz, 220-300 GHz
0.01
1E-3
1E-4
1E-5
1E-6
0.0
0.2
0.4
0.6
0.8
1.0
Frequency, THz
Geometric path losses are LOW
due to short wavelengths.
4 mW transmitter power sufficient for 10 Gb/s
transmission over 500 meters range
given 20 cm diameter antennas
Bit rate
carrier frequency
F
Distance
atmospheric loss
Dant, trans
Dant, rcvr
bits/symbol
kT
Prec
∆f
transmission
atmospheric loss
Ptransmitter
1.00E+10
1/sec
1.50E+11
Hz
10
dB
5.00E+02
m
4.00E-03
dB/m
0.2
m
0.2
m
1
-173.83 dBm (1Hz)
-48.27
dBm
1.00E+10
Hz
-51.64
2
dB
3.4
mW
receiver noise figure
transmission range
dB loss per unit distance
transmit antenna diameter
receive antenna diameter
received power at 10^{-9} B.E.R
RF channel bandwidth required
geometric path loss, dB
total atmospheric loss, dB
required transmitter power
How Do We Improve the Bandwidth of Bipolar Transistors ?
 kT

1
kT
  base   collector  C je
 Cbc 
 Rex  Rcoll 
2f
qI E
 qI E

Thinner base, thinner collector
 higher f , but higher RbbCcb , RexCcb …
what parameters are really important in HBTs ?
how do we improve HBT performance ?
Rodwell
HBT scaling: layer thicknesses
2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,
WE
WEB
LE
emitter
base
x
reduce Tb by 2:1
b improved 2:1
reduce Tc by 2:1
c improved 2:1
note that Ccb has been doubled
..we had wanted it 2:1 smaller
base
collector
WC
WBC
 b  Tb2 / 2 Dn
 b  Tc / 2vsat
Assume WC ~ WE
's
Rodwell
HBT scaling: lithographic dimensions
2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,
Rbb  Rgap  Rspread  Rcontact
Base Resistance Rbb must remain constant
 Le must remain ~ constant
 Rcontact
  sheet  c ,vertical 2 LE
Ccb/Area has been doubled
..we had wanted it 2:1 smaller
…must make area=LeWe 4:1 smaller
must make We & Wc 4:1 smaller
WE
WEB
LE
emitter
base
x
reduce collector width 4:1
reduce emitter width 4:1
keep emitter length constant
's
base
collector
WC
WBC
Assume WC ~ WE
HBT scaling: emitter resistivity, current density
2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, 's
Rodwell
Emitter Resistance Rex must remain constant
but emitter area=LeWe is 4:1 smaller
resistance per unit area must be 4:1 smaller
Assume WC ~ WE
Collector current must remain constant
but emitter area=LeWe is 4:1 smaller
and collector area=LcWc is 4:1 smaller
current density must be 4:1 larger
WE
WEB
LE
emitter
base
increase current density 4:1
reduce emitter resistivity 4:1
x
base
collector
WC
WBC
Rodwell, IEEE Trans. Electron Devices, Nov. 2001
Scaling Laws for fast HBTs
Required proportion al change in HBT parameters in order to obtain
a  : 1 increase in bandwidth in an arbitrary circuit
For some device structures , but not all ,
the base contact resistivit y  v ( - cm 2 ) must also scale as   2
Electronics
for GigaHertz Communication
Optical Transmitters / Receivers are Mixed-Signal ICs
Wideband Optical Transceiver
address
detect
O/E, E/O interfaces
buffer
A
DMUX
D
PLL
Switch
route
clock
MUX
Wideband mm-Wave Transceiver
TIA: small-signal
mm-wave interfaces LIA: often limiting
A
D
Rc
Rc
PLL
I
Q
power
amplifier
Q1
DMUX
D
Rf
Q2
DMUX
I
Q
A
Rf
Q2
I2
I2
I1
I
Q
Q1
electronic
MUX/CMU & DMUX/CDR:
or optical
mostly digital
D
A
I
MUX
Switches:
network protocols,
digital control, fast ICs,
optical, electronic switches
I1 D
A
Q
Small-signal cutoff frequencies (f, fmax) are ~ predictive of analog speed
Limiting and digital speed much more strongly determined by (I/C) ratios
InP HBT has been well-optimized for f & fmax, less well for digital speed
How do we improve logic speed ?
Gate Delay Determined by :
Depletion capacitanc e charging
through the logic swing
 VLOGIC 

Ccb  Cbe,depletion 
 IC 
Depletion capacitanc e charging
through the base resistance
Rbb Ccb  Cbe,depletion 
Supplying base  collector
stored charge
through the base resistance
 IC 

Rbb  b   c 
 VLOGIC 
The logic swing must be at least
 kT

VLOGIC  6
 Rex I c 
 q

out
out
in
in
clock
clock
clock
clock
Delay not well correlated with f .
VLOGIC
I C Ccb  Cbe,depl  is 60% - 80% of total.
High I C / Ccb  is a key HBT design objective.
 Acollector  TC 





 Aemitter  2veffective 
Rex must be very low for low Vlogic at high J e
Ccb VLOGIC VLOGIC

IC
2VCE ,min
InP logic barely faster tha n SiGe :
need to design for clock speed, not f & f max
Technology Roadmaps for 40 / 80 / 160 Gb/s
Challenges with Scaling:
Collector-base scaling
Mesa HBT: collector under base contacts.
Base contacts have nonzero resistivity → sets minimum contact size
Solution: reduce base contact resistivity
Solution: decouple base & collector dimensions
e.g. buried SiO2 in junction (SiGe), undercut-mesa (InP)
Emitter Ohmic Resistivity:
must improve in proportion to square of speed improvements
Current Density:
increases rapidly
device heating, current-induced dopant migration, dark-line defect formation
SiGe at 5*105 A/cm2, InP at 1*105
Loss of breakdown voltage
InP superior to SiGe at equal speed
Yield
InP HBT processes must reach yield sufficient for DMUX/CMU
progressively more difficult at submicron dimensions
Low Ccb InP HBT structures
transferred-substrate
Allows deep submicron collector scaling
high mm-wave gains
low yield at deep submicron scaling
mm-wave device, not mixed-signal
undercut-collector
emitter
base contact
undercut
collector junction
InGaAs
collector
InGaAs base
InP collector
collector
contact
InGaAs subcollector
InP subcollector
Pursued by several research groups
Also has uncertain yield at submicron
geometries
SI substrate
Narrow-mesa with ~1E20 carbon-doped base
The conservative III-V device structure
Yet, I assert that even this device is not
viable of mass manufacturing if
> 3000 transistors per IC are sought
Need improved device structures for high yield at 0.1 mm scaling
Transferred-Substrate HBTs
UCSB
ONR
220 GHz On-Wafer Network Analysis
Miguel Urteaga
140-220 GHz network analysis
HP8510C network analyzer
& Oleson Microwave Lab
frequency Extenders
GGB waveguide-coupled probes
75-100 GHz network analysis
GGB waveguide-coupled probes
HP W-band test set
1-50 GHz network analysis
GGB coax-connectorized probes
HP 0.045-50 GHz test set
Accurate measurements are not easy
HBT Ccb is very small (~5 fF)
→ S12 easily masked by probe-probe coupling
increase probe separation: reference plane extensions
On-wafer LRL calibration standards
ultra-thin microstrip for reduced mode coupling
Submicron InAlAs/InGaAs HBTs:
Unbounded (?!?) Unilateral power gain 45-170 GHz
UCSB
ONR
Miguel Urteaga
40
unbounded
U
35
30
U
emitter
RF Gains
25
20
15
MAG/MSG
h21
10
5
0
-5
1E10
1E11
1E12
collector
Freq.
Emitter: 0.3 x 18 mm2,
Collector: 0.7 x 18.6 mm2
Ic = 5 mA, Vce = 1.1 V
gain resonances
likely due to IMPATT effects
Rodwell, Int. Symp. Compound Semiconductors, Tokyo, Oct. 2001
Urteaga, Int. Journal High Speed Electronics and Systems, to be published
UCSB
175 GHz Single-Stage Amplifier
Miguel Urteaga
10
S21
S11
S22
50
0.2pF
5
80
1.2ps
30
0.2ps
80
1.2ps
50
30
1.2ps
0
50

0.6ps
dB
IN
OUT
-5
-10
-15
-20
140
150
160
170
180
190
200
Freq. (GHz)
6.3 dB gain at 175 GHz
210
220
Deep Submicron Bipolar Transistors
for 140-220 GHz Amplification
Transistor Gains, dB
30
unbounded U
U
U
20
MSG/MAG
10
H
21
0
10
100
1000
Frequency, GHz
8
6
4
S21, dB
Miguel Urteaga
raw 0.3 mm transistor: 6-11 dB power gain @ 200 GHz
40
2
-2
1-transistor amplifier:
6.3dB @ 175 GHz
-4
140
150
0
160
170
180
190
200
210
220
Frequency, GHz
10
gain, dB
UCSB
0
-10
-20
-30
140
3-transistor amplifier:
8 dB @ 195 GHz
150
160
170
180
190
Frequency (GHz)
200
210
220
UCSB
InGaAs/InP DHBT, 3000 Å InP collector
Sangmin Lee
2
40
I step = 20 mA
fmax = 462 GHz,
ft = 139 GHz
b
Gains (dB)
IC (mA)
30
1
BVCEO = 8 V at JE =5*104 A/cm2
2
4
VCE (V)
6
20
343
395
10
0
0
U
8
h21
139
462
0
1
10
100
1000
Frequency (GHz)
0.5 mm x 8 mm emitter (mask)
0.4 mm x 7.5 mm emitter (junction)
1.0 mm x 8.75 mm collector
High Current, High Breakdown Voltage InP DHBT
140
A =128 um
120
2
E
14
12
10
80
Ic, m A
Ic, mA
100
60
8
6
4
40
2
0
-1
20
0
1
2
3
4
5
6
7
Vcb, V
0
0
2
4
6
8
10
Vcb, V
30
AE=128um2
U, MSG/MAG, dB
25
8-finger device
8 x ( 1 mm x 16 mm emitter )
8 x ( 2 mm x 20 mm collector )
IC=100mA
20
15
Vcb=2.9V
MSG/MAG
U
10
5
0 0
10
fmax=330 GHz
10
1
10
2
Frequency, GHz
10
3
ARO
MURI
UCSB
W band 128 mm2 power amplifier
common base PA
0.5mm x 0.4 mm, AE=128 mm2
Bias: Ic=78 mA, Vce=3.6 V
20
10
10
S21
GT
5
8
10
6
5
4
0
2
S11
-15
T
-10
-20
-25
-30
80
90
frequency, GHz
100
110
G , dB
-5
Pout, dBm
S22
0
S11, S21, S22
Pout
15
-5
0
-15
-10
-5
0
5
10
Pin, dBm
f0=85 GHz, BW3dB=28 GHz,GT=8.5 dB, P1dB=14.5 dBm, Psat=16dBm
15
High Speed Amplifiers
18 dB, DC--50+ GHz
20
S21
15
>397 GHz
gain x bandwidth
from 2 HBTs
10
5
0
S11
-5
-10
S22
-15
-20
0
10
20
30
40
50
8.2 dB, DC-80 GHz
10
Gains, dB
S
21
5
0
S
-5
11
-10
S
22
-15
0
10
20
30
40
50
Frequency, GHz
60
70
80
UCSB
Dino Mensa
PK Sundararajan
Ultra Wideband Mesa
InP/InGaAs/InP DHBTs
UCSB / IQE
Mattias Dahlstrom (UCSB)
Amy Liu (IQE)
30
500 Ohm/square base sheet resistance
< 2*10-7 Ohm-cm2 base contact resistance
25
21
Gain (dB) H , U
2000 Å InP collector
300 Å InGaAs base
8E19 to 5E19 graded C base doping
InAlAs/InGaAs base-collector grade.
20
15
f =282 GHz
t
10
f
=480 GHz
max
5
0
10
7.5 V Breakdown
282 GHz f
>450 GHz fmax,
operation to 500 kA/cm2 at 1.7 volts
10
10
11
frequency (GHz)
10
12
87 GHz HBT master-slave latch UCSB
PK Sundararajan,
Zach Griffith
200 GHz logic program
InAlAs /InGaAs/InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO
200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
87 GHz input, 43.5 GHz output
-0.06
-0.08
V
out
(Volts)
-0.1
-0.12
-0.14
-0.16
-0.18
-0.2
22
22.02 22.04 22.06 22.08
time (nsec)
22.1
22.12 22.14
8 GHz S ADC
UCSB
PK Sundararajan,
Zach Griffith
200 GHz logic program
Technology
0.7 um InAlAs /InGaAs/InP MESA DHBT
400 Å base, 2000 Å collector,
9 V BVCEO, 200 GHz ft, 180 GHz fmax
2.5 x 105 A/cm2 operation
Design
simple 2nd-order gm-C topology
comparator is 87 GHz MSS latch
integration by capacitive loads
3-stage comparator, RTZ gated DAC
Results
133 dB (1 Hz) SNR at 74 MHz
equivalent to ~8.8 bits at 200 MS/s
975 kHz FFT bin size
8 GHz clock rate
65.5 MHz signal
64:1 oversampling ratio
InP vs. Si/SiGe HBTs: recent experience at 40 Gb/s
40 Gb/s IC development during internet bubble
7 of my ex-Ph.D. students involved, at 4 different companies
personally actively involved as consultant
InP HBT technology
1 mm design-rule processes easily developed,
good reliability, yield ok for 2000 HBTs (not more),
170 GHz f, fmax , 7 volt Vbr, 3 mA (min) device, 60 GHz clock
Resulting ICs
TIA, LIA, 6 V differential modulator driver: quite successful
MUX/CMU, DMUX/CDR: limited to 4:1 (yield, power)
SiGe necessary for 16:1 standards-compliant MUX & DMUX
market is presently very small
InP requires lower NRE than SiGe
InP critically needs:
higher integration scales, scaling for speed & power
Very strong features of SiGe-bipolar transistors
High current density
10 mA/mm2
T-shaped polysilicon emitter
0.25 mm junction
wide contact
low resistance, high yield
Thin intrinsic base: low b
Thick extrinsic base: low Rbb
Low Ccb collector junction
collector pedestal
CVD/CMP SiO2 planarization
regrown poly extrinsic base
High-yield, planar processing
high levels of integration
LSI and VLSI capabilities
SiGe clock rates up to 65 GHz
Much more complex ICs than feasible in InP HBT
InP HBT must reach higher integration scales or will cease to compete
InP vs. Si/SiGe HBTs: materials vs. scaling advantages
Advantages of InP
~20:1 lower base sheet resistance,
~5:1 higher base electron diffusivity
~3:1 higher collector electron velocity,
~4:1 higher breakdown-at same f.
Disadvantage of InP: archaic mesa fabrication process
Presently only scaled to ~ 1 um (production)
large emitters, poor emitter contact:
low current density: 2 mA/um2
high collector capacitance
nonplanar device - low yield
low integration scales
InP HBT limits to yield: non-planar process
Emitter contact
Failure
modes
liftoff failure:
emitter-base
short-circuit
emitter
base contact
base
base
sub collector
S.I. substrate
sub collector
S.I. substrate
Etch to base
base
excessive
emitter undercut
sub collector
base contact
S.I. substrate
base
Liftoff base metal
base contact
emitter
contact
sub collector
base contact
S.I. substrate
base
sub collector
S.I. substrate
planarization failure: interconnect breaks
Emitter planarization, interconnects
base
base
sub collector
S.I. substrate
sub collector
S.I. substrate
Yield degrades as emitters are
scaled to submicron dimensions
MBE growth of Polycrystalline n+ InAs
Dennis Scott
SiGe HBT process: extensive use of non-selective-area poly-Si regrowth
Can a similar technology be developed for InP ?
Polycrystalline InAs grown on SiN:
• Doping = 1.3 1019 cm-3,
Mobility = 620 cm2/V•s
Poly InAs:Si Doping vs. Temp
19
2.2 10
2 10
• Results in doping-mobility
product of 81021 (V •s •cm)-1
19
1.8 10
19
Doping
InGaAs lattice matched to InP:
• Doping = 1.0 1019 cm-3,
Mobility = 2200 cm2/V•s
• Results in doping-mobility
product of 221021 (V •s •cm)-1
19
1.6 10
19
1.4 10
19
1.2 10
1 10
19
8 10
18
6 10
18
945
950
955
960
965
Temp
Polycrystalline InAs has potential as an extrinsic emitter contact.
970
975
980
985
1) Epitaxial Growth,
Fe implant isolation
Process Flow:
Single-polyregrowth
InP HBT
2) Deposit Pd/W base Ohmics.
Encapsulate with Si3N4
Etch base-collector junction
base
base
N- collector
N- collector
N+ subcollector
N+ subcollector
S.I. substrate
S.I. substrate
3) Passivate with Si3N4
Etch emitter window through base
Form emitter SiN sidewalls
top view
emitter
junction
extrinsic
emitter
and
contact
subcollector
isolation
implant
mask
4) Regrow polycrystalline emitter.
Deposit emitter metal.
Etch through emitter
emitter contact
regrown
InAlAs/InAs
emitter*
Si N
3 4
base contact
Si N
3 4
base
contact
N- collector
N+ subcollector
S.I. substrate
collector
contact
base
contact
base
contact
Si N
3 4
N- collector
N+ subcollector
S.I. substrate
5) Recess etch and deposit
collector contacts
N- collector
N+ subcollector
S.I. substrate
emitter contact
regrown
InAlAs/InAs emitter*
Si N
3 4
base contact
collector
contact
*monocrystalline where
grown on semiconductor,
polycrystalline where
grown on silicon nitride
Regrown-Poly-InAs-Emitter HBT
1
1.0 10
AE = 0.8 x 15 um
2
I b = 100uA/step
0
0
6.0 10
c
I (mA)
8.0 10
0
4.0 10
0
2.0 10
0
0.0 10
0
1
2
3
4
V (V)
ce
Ib, Ic (mA)
2
10
2
10
1
10
0
10
-1
10
-2
10
-3
10
-4
Gummel for 0.8x15 um Emitter
Ic
Ib
0
0.2
0.4
0.6
0.8
Vbe (volts)
1
1.2
Dennis Scott
Submicron Scaling of InP HBTs
InP HBTs are a mixed-signal, not a MIMIC technology
for MIMICs, sub-0.1-mm InP HEMTs are hard to beat
mixed-signal is fiber ICs, ADCs, DACs, digital frequency synthesis
these are 1000 -- 40,000 transistor ICs
InP HBTs are struggling to compete with SiGe HBT
application demands transistor counts near/beyond yield limits
large emitter junctions→ high current → power near acceptable limits
no decisive speed advantage in relevant circuits: digital logic
materials advantages being squandered by inadequate scaling
InP HBTs can be scaled to operate at 160 Gb/s
key is scaling emitter to 0.2 mm, collector to 0.4 mm
contact resistivities challenging but feasible; yield is key concern
Critically needed for InP HBTs
highly scaled process: 0.2 mm emitters, 0.4 mm collectors
highly planar and high-yield fabrication processes
small emitter junctions (0.2 mm x 0.5 mm) for acceptable power
In Case of
Questions
What HBT parameters determine logic speed ?
Cje
V/ I
V/ I
(kT/q) I
Rex
Rbb
total
Ccbx
33.5%
1.4%
-1.3%
10.2%
43.8%
b+c ) ( I/V)
Ccbi
6.7%
0.1%
0.1%
6.8%
38%
total
27.8%
0.4%
0.3%
2.8%
31.3%
68.4%
12.3%
2.5%
0.1%
16.7%
100.0%
12.3%
0.5%
0.9%
3.7%
17.5%
Sorting Delays by capacitanc es :
44% charging C je , 38% charging Ccb , only 18% charging Cdiff (e.g.  b   c )
Sorting Delays by resistance s and transit t imes :
68% from Vlogic / I c , 12% from ( b   c ), 17% from Rbb
Rex has very strong indirect effect, as Vlogic  6  kT / q  I C Rex 
Caveats:
assumes a specific UCSB InP HBT (0.7 um emitter, 1.2 um collector 2kÅ thick, 400 Å base, 1.5E5 A/cm^2)
ignores interconnect capacitance and delay, which is very significant
Yoram Betser, Raja Pullela
Accurate Transistor Measurements Are Not Easy
• Submicron HBTs have very low Ccb (< 5 fF)
• HBT S12 is very small
230 mm
230 mm
• Standard 12-term VNA calibrations do not
correct S12 background error due to
probe-to-probe coupling
Solution
Embed transistors in sufficient length of
transmission line to reduce coupling
Transistor in Embedded in LRL Test Structure
Place calibration reference planes at transistor
terminals
Line-Reflect-Line Calibration
Standards easily realized on-wafer
Does not require accurate characterization of
reflect standards
Characteristics of Line Standards are well
controlled in transferred-substrate microstrip
wiring environment
Corrupted 75-110 GHz measurements due to
excessive probe-to-probe coupling
Can we trust the calibration ?
Miguel Urteaga
75-110 GHz calibration looks Great
140-220 GHz calibration looks OK
S11 of open
About 0.1 dB / 3o error
S11 of through
About –40 dB
S11 of short
S11 of through
S11 of open
freq (75.00GHz to 110.0GHz)
freq (140.0GHz to 220.0GHz)
0.30
Probe-Probe coupling
is better than –45 dB
-40
-45
0.25
S21 of through line is
off by less than 0.05 dB
0.20
0.15
0.10
-50
0.05
-55
0.00
-60
-0.05
-0.10
-65
-0.15
-70
140
75
80
85
90
95
freq, GHz
100
105
150
160
170
180
110
freq, GHz
190
200
210
220
Negative Unilateral Power Gain ???
Can U be Negative?
YES, if denominator is negative
This may occur for device with a negative output
conductance (G22) or some positive feedback (G12)
U
Y21  Y12
2
4G11G 22  G 21G12 
What Does Negative U Mean?
Device with negative U will have infinite Unilateral
Power Gain with the addition of a proper source or load
impedance
2-port
Network
AFTER Unilateralization
• Network would have negative output resistance
• Can support one-port oscillation
• Can provide infinite two-port power gain
U
Y21  Y12
GL
2
4G11 G 22  G L   G 21G12 
Select GL such that denominator is zero:
U
Simple Hybrid-  HBT model will NOT show negative U
Rodwell
Scaling Laws, Collector Current Density, Ccb charging time
Collector Field Collapse (Kirk Effect)
Vcb    ( J / vsat  qN d )(Tc2 / 2 )
base
emitter
sub
collector
collector
Collector Depletion Layer Collapse
Vcb,min    (qN d )(Tc2 / 2 )
base
emitter
sub
collector
collector
 J max  2vsat (Vcb  Vcb,min  2 ) / Tc2
Note that Vbe   , hence (Vcb   )  Vce
Ccb VLOGIC / I C  Acollector Tc VLOGIC
VLOGIC  Acollector  TC 



IC  
VCE  VCE ,min   Aemitter  2vsat 
Collector capacitance charging time is reduced
by thinning the collector while increasing current
Why isn't base+collector transit time so important ?
Under Small - Signal Operation :
Q base
dI C
( b   c ) I C
 ( b   c )I C  ( b   c )
Vbe 
Vbe
dVbe
kT / q
Under Large - Signal Operation :
( b   c ) I dc
Q base  ( b   c ) I C 
VLOGIC
VLOGIC
Large - signal diffusion capacitanc e reduced by ratio of
 VLOGIC 

, which is ~ 10 : 1
 kT / q 
Depletion capacitanc es see no such reduction
HBT distributed amplifier
AFOSR
11 dB, DC-87 GHz
15
S
10
21
Gains, dB
5
0
-5
S
-10
22
S
11
-15
-20
0
20
40
60
Frequency, GHz
80
TWA with internal ft-doubler cells
UCSB
PK Sundararajan